Drivven, Inc.
Throttle Driver Module Kit
© Drivven, Inc. 2009
• Throttle Driver Module Kit User’s Manual • D000017 • Rev B
16
Sub VI Documentation
throttle_revb.vi
This VI is for interfacing directly with the Drivven Throttle Driver module and for providing a
control interface to the LabVIEW RT level.
The FPGA VI must be placed within a Single Cycle Loop (SCL) of a LabVIEW FPGA block
diagram. The SCL must execute at the default clock rate of 40 MHz.
The FPGA VI requires a pre-synthesized netlist file having a matching name and an extension of
.ngc. The netlist file must be located in the same directory as the matching VI. The installer will
place this file in the LabVIEW addons directory along with the FPGA VI.
The PinInput and PinOutput clusters are wired to LabVIEW FPGA I/O nodes which are configured
for a cRIO controller chassis or a cRIO R-Series expansion chassis. Refer to the LabVIEW
FPGA documentation for details about creating and configuring FPGA I/O nodes.
Connector Pane
Controls and Indicators
ThrottleControl
This cluster contains the main enable Boolean, watchdog Boolean and
PWM parameters for each H-Bridge channel.
ModuleEnable
If a throttle driver module is inserted in the proper slot, externally
powered, and ModuleEnable is TRUE, then software begins communicating with
the module and allows the module to operate. When the module is properly
recognized, then the ModulePresent Boolean within the ThrottleData cluster will
be set to TRUE.
WatchdogIn
WatchdogIn must be toggled at a rate greater than or equal to
10Hz. This should only be performed at the RT level. DO NOT toggle the
watchdog at the FPGA level. Toggling the watchdog at the FPGA level would
bypass the software safety feature for which it is intended.
Throttle1Period
The time period between leading edges of the PWM pulse train
to h-bridge circuit 1. Throttle1Period is entered in terms of 4 MHz clock ticks.
This provide a maximum period of 8.192 milliseconds or a minimum frequency of
122 Hz, and a resolution of 250 nsec.
Throttle2Period
The time period between leading edges of the PWM pulse train
to h-bridge circuit 2. Throttle2Period is entered in terms of 4 MHz clock ticks.
This provides a maximum period of 8.192 milliseconds or a minimum frequency
of 122 Hz, and a resolution of 250 nsec.
Throttle1PulseWidth
The time during each Throttle1Period in which the PWM
pulse train to h-bridge circuit 1 is active. This value is signed, and represents
direction of current flow through the h-bridge circuit. A positive value represents
positive current flowing from terminal H1B to H1A. Throttle1PulseWidth is
entered in terms of 4 MHz clock ticks. While Throttle1PulseWidth is 0, h-bridge
circuit 1 will remain inactive. While Throttle1PulseWidth is greater than or equal
to Throttle1Period, h-bridge circuit 1 will remain fully active. This condition
