8
|
ni.com
|
NI 5782R User Manual and Specifications
NI 5782 Component-Level Intellectual Property
(CLIP)
The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL
IP integration. NI FlexRIO devices support two types of CLIP: user-defined and socketed.
•
User-defined CLIP
allows you to insert HDL IP into an FPGA target, enabling VHDL code
to communicate directly with an FPGA VI.
•
Socketed CLIP
provides the same IP integration functionality of the user-defined CLIP, but
also allows the CLIP to communicate directly with circuitry external to the FPGA. Adapter
module socketed CLIP allows your IP to communicate directly with both the FPGA VI and
the external adapter module connector interface.
The following figure shows the relationship between an FPGA VI and CLIP.
Figure 4.
CLIP and FPGA VI Relationship
Ad
a
pter Mod
u
le
CLIP
S
ocket
L
ab
VIEW
FPGA VI
U
s
er-Defined
CLIP
NI FlexRIO FPGA Mod
u
le
FPGA
Exter
n
a
l
I/O Connector
Ad
a
pter
Mod
u
le
S
ocketed
CLIP
U
s
er-Defined
CLIP
Fixed I/O
DRAM 0
CLIP
S
ocket
S
ocketed
CLIP
DRAM 1
CLIP
S
ocket
S
ocketed
CLIP
Fix
ed I/O
Fix
ed I/O
DRAM0
DRAM1