NI 5782R User Manual and Specifications
|
© National Instruments
|
7
Block Diagram
Figure 3 shows the NI 5782 block diagram and signal flow to and from the NI 5782
component-level intellectual property (CLIP) by way of the adapter module and the
corresponding NI 5782 Multiple Sample CLIP in LabVIEW FPGA.
Figure 3.
NI 5782 Connector Signals and NI 5782 CLIP Signal Block Diagram
PFI <0..
3
> Rd D
a
t
a
L
ab
VIEW FPGA CLIP
NI 57
8
2 Ad
a
pter Mod
u
le
PFI <0..
3
> Wr D
a
t
a
DIO Port <0..1> Write En
ab
le
PFI <0..
3
> Write En
ab
le
Trigger Inp
u
t
S
PI Re
a
d
S
PI Write
S
PI Addre
ss
S
PI Write D
a
t
a
S
PI Re
a
d D
a
t
a
S
PI Device
S
elect
Initi
a
liz
a
tion Done
Reiniti
a
lize
Config
u
r
a
tion Error
Sa
mple Clock
S
elect
Sa
mple Clock Commit
S
PI Idle
D
a
t
a
Clock
AI 0 D
a
t
a
N
AI 1 D
a
t
a
N
AO 0 D
a
t
a
N
AO 0 D
a
t
a
N–2
AI 0 D
a
t
a
N–1
AI 1 D
a
t
a
N–1
AO 0 D
a
t
a
N–1
AO 0 D
a
t
a
N–
3
AO 1 D
a
t
a
N
AO 1 D
a
t
a
N–1
AO 1 D
a
t
a
N–2
AO 1 D
a
t
a
N–
3
D
a
t
a
Clock
D
a
t
a
Sa
mple
Clock
Clock
B
u
ffer
Intern
a
l
Reference
Clock
Clock
S
ynthe
s
izer
S
witch
S
witch
CLK IN
AUX I/O
TRIG
AI 0
AI 1
AO 0
AO 1
S
witch
Clock
DAC
Interf
a
ce
ADC
Interf
a
ce
IOMod
S
yncClock
ADC
DAC
An
a
log
Front End
B
us
Tr
a
n
s
l
a
tor
B
us
Tr
a
n
s
ceiver
2
4
DIO Port 0 Rd D
a
t
a
<0..
3
>,
DIO Port 1 Rd D
a
t
a
<0..
3
>
DIO Port 0 Wr D
a
t
a
<0..
3
>,
DIO Port 1 Wr D
a
t
a
<0..
3
>
8
8
4
4
An
a
log
Front End
An
a
log
Front End
An
a
log
Front End
AD9512
S
ynthe
s
izer Locked
An
a
log front
end (FE)
S
witche
s
ADC
s
AD9512
S
PI Engine
Interf
a
cing
with:
DAC
s
