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National Instruments Corporation
13
NI 1483R User Guide and Specifications
NI 1483 Component-Level Intellectual Property (CLIP)
The LabVIEW FPGA Module includes a feature for HDL IP integration called CLIP. NI FlexRIO
devices support two types of CLIP: user-defined and socketed.
•
A user-defined CLIP allows you to insert HDL IP into an FPGA target, enabling VHDL code to
communicate directly with an FPGA VI.
•
NI FlexRIO devices also support socketed CLIP, which provides the same IP integration
functionality of the user-defined CLIP, while also allowing the CLIP to communicate directly with
circuitry external to the FPGA. Adapter module socketed CLIP allows your IP to communicate
directly with both the FPGA VI and the external adapter module connector interface.
Figure 10 shows the relationship between an FPGA VI and the CLIP.
Figure 10.
CLIP Relationship
The NI 1483 ships with socketed CLIP that is used to add module I/O to the LabVIEW project.
The NI-developed NI 1483 CLIP supports Base, Medium, Full, and 80-bit Camera Link configurations.
Camera Link data outputs on ten 8-bit Camera Link ports (A through J) along with flags, all of which
are synchronous to the user-selected Image Data Clock. The CLIP also provides access to the Camera
Link serial interface, four camera control lines, four TTL I/O lines, two isolated inputs, and inputs for a
quadrature encoder.
Refer to the
NI FlexRIO Adapter Module Support Help
topic of the
LabVIEW Help
for information
regarding NI FlexRIO CLIP, configuring the NI 1483 with a socketed CLIP, and a list of available
socketed CLIP and provided signals.
Ad
a
pter Module
CLIP
S
ocket
L
ab
VIEW
FPGA VI
U
s
er-Defined
CLIP
NI FlexRIO FPGA Module
FPGA
Exter
n
a
l
I/O Connector
Ad
a
pter
Module
U
s
er-Defined
CLIP
Fixed I/O
S
ocketed
CLIP
DRAM 1
CLIP
S
ocket
DRAM 0
CLIP
S
ocket
S
ocketed
CLIP
S
ocketed
CLIP
Fix
ed I/O
DRAM0
DRAM1
Fix
ed I/O
