NAT-AMC-ZYNQUP-FMC
T
ECHNICAL
R
EFERENCE
M
ANUAL
V1.1
H
ARDWARE
- 39 -
5.3.2.
J3: JTAG Programming Header
Connector J3 offers a JTAG programming interface.
Figure 8
–
J3: JTAG Programming Header
14
13
2
1
Table 19
–
J3: JTGA Programming Header
–
Pin Assignment
Pin #
Signal
Signal
Pin #
1
V_PROG
JTAG_DISABLE
2
3
FPGA_TMS
GND
4
5
FPGA_TCK
GND
6
7
FPGA_TDO
GND
8
9
FPGA_TDI
GND
10
11
nc
GND
12
13
PS_ARM_SRST
GND
14
5.3.3.
J6: Memory Connector
Connector J6 offers the option to connect additional memory, e.g. RLDRAM, QDR4-SRAM, or
another DDR4 RAM.
The memory to FPGA pin assignment varies depending on the installed memory type, so a
general specification cannot be given. Please refer to chapter 4.1.2.2 Memory for details.