4-8
Computer Group Literature Center Web Site
Functional Description
4
typical usage of the SRAM can be a descriptor RAM for the Gigabit
Ethernet ports.
General-Purpose Timers/Counters
There are four 32-bit wide timers/counters on the MV64360. Each
timer/counter can be selected to operate as a timer or as a counter. The
timing reference is based on the MV64360 Tclk input, which is set at
133 MHz. Each timer/counter is capable of generating an interrupt. Refer
to the MV64360 Data Sheet, listed in
Appendix C, Related
Documentation
, for additional information and programming details.
Watchdog Timer
The MV64360 internal watchdog timer is a 32-bit count-down counter that
can be used to generate a non-maskable interrupt or reset the system in the
event of unpredictable software behavior. After the watchdog timer is
enabled, it becomes a free running counter that must be serviced
periodically to keep it from expiring. Refer to the MV64360 Data Sheet,
listed in
Appendix C, Related Documentation
, for additional information
and programming details.
I
2
O Message Unit
I
2
O compliant messaging for the MVME6100 board is provided by an I
2
O
messaging unit integrated into the MV64360 system controller. The
MV64360 messaging unit includes hardware hooks for message transfers
between PCI devices and the CPU. This includes all of the registers
required for implementing the I
2
O messaging, as defined in the Intelligent
I/O (I
2
O) Standard specification. For additional details regarding the I
2
O
messaging unit, refer to the MV64360 Data Sheet, listed in
Appendix C,
Related Documentation
.
Four Channel Independent DMA Controller
The MV64360 incorporates four independent direct memory access
(IDMA) engines. Each IDMA engine has the capability to transfer data
