CNFG and ENV Commands
6-11
6
ROM Next Access Length (0 - 15) = 0?
The value programmed into the MPC105 “ROMNAL” field (Memory
Control Configuration Register 8: bits 28-31) to represent wait states
in access time for nibble (or burst) mode ROM accesses. The lowest
allowable ROMNAL setting is $0; the highest allowable is $F. The
value to enter depends on processor speed; refer to your
Processor/Memory Mezzanine Module User’s Manual for appropriate
values. The default value varies according to the system’s bus clock
speed.
DRAM Parity Enable [On-Detection/Always/Never - O/A/N] = O?
L2 Cache Parity Enable [On-Detection/Always/Never - O/A/N] = O?
PCI Interrupts Route Control Registers (PIRQ0/1/2/3) = 0A0B0E0F?
Initializes the PIRQx (PCI Interrupts) route control registers in the
IBC (PCI/ISA bus bridge controller). The ENV parameter is a 32-bit
value that is divided by 4 to yield the values for route control registers
PIRQ0/1/2/3. The default is determined by system type. For details on
PCI/ISA interrupt assignments and for suggested values to enter for
this parameter, refer to the Maskable Interrupts section of Chapter 4 in
the MVME1603/ MVME1604 Programmer’s Reference Guide.
O
DRAM parity is enabled upon detection. (Default)
A
DRAM parity is always enabled.
N
DRAM parity is never enabled.
O
L2 Cache parity is enabled upon detection. (Default)
A
L2 Cache parity is always enabled.
N
L2 Cache parity is never enabled.
Содержание MVME1603
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