33-16
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Part V. The Communications Processor Module
33.7.2 Pulsed Handshake Mode
The pulsed handshake mode, shown in Figure 33-12, supports a Centronics-compatible
interface.
Figure 33-12. Pulsed Handshake Full Cycle
¥
When sending, the PIP generates STB when data is ready in the PIP output latch and
the previous transfer is acknowledged. The setup time and the pulse width of STB
are programmable.
¥
When receiving, the PIP uses STB to latch input data and ACK to acknowledge the
transfer. The timing of ACK is also programmable.
The core conÞgures the PIP to implement a Centronics protocol by programming the PIP
conÞguration (PIPC) register. When the PIP is under CP control, timing attributes are set in
PTPR. Transmit and receive errors are reported through BDs. For information about
supporting a Centronics interface, see Section 33.9, ÒImplementing Centronics.Ó
CP/Core
In Use
STB
Tx Data
CP/Core
In Use
ACK
Rx Data
Byte A
Byte B
Byte A
Byte B
PIP Transmit
PIP Receive
Write from Handshake
Control Logic (DIR = OUT)
Latch
Latch
I/O
Pin
Write from CP
Read from CP
DIR = Output
Peripheral Bus
Содержание MPC860 PowerQUICC
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