Motorola M68MPBF333, Руководство пользователя

Страница: 34 / 58

MEVB SUPPORT INFORMATION
4-4 M68MPB333UM/D
Table 4-5. Logic Analyzer Connector J11 Pin Assignments
Pin Mnemonic Signal
1 +5V +5 VDC POWER – Input voltage (+5Vdc @ 1.0 A) used
by the MEVB logic circuits. (To make this pin a no
connection, remove the jumper from jumper header W9
on the MPFB.)
2 SPARE No connection
3 DS DATA STROBE – Active-low output signal. During a
read cycle, indicates that an external device should
place valid data on the data bus. During a write cycle,
indicates that valid data is on the data bus.
4 – 19 D15 – D0 DATA BUS 15 – 0 – 16 bits of the MCU bi-directional
data bus lines.
20 GND GROUND
Table 4-6. Logic Analyzer Connector J12 Pin Assignments
Pin Mnemonic Signal
1, 2 SPARE No connection
3 CLKOUT SYSTEM CLOCK OUT – Output signal that is the MCU
internal system clock.
4 BERR BUS ERROR – Active-low signal that indicates a
memory access error has occurred.
5 BKPT /
DSCLK
BREAKPOINT – Active-low input signal that signals a
hardware breakpoint to the CPU.
Development Serial Clock – Clock input signal for
background debug mode.
6 FREEZE
QUOT
FREEZE – Output signal that indicates the CPU has
acknowledged a breakpoint.
QUOTIENT OUT – Output signal that furnishes the
quotient bit of the polynomial divider for test purposes.
7 LAT-DSO
(Latched IPIPE0)
LATCHED INSTRUCTION PIPE 0 – Latched output
signal of the first state of IPIPE0 for CPU16-based
MCUs; indicates instruction pipeline activity.
Logic low for CPU32-based MCUs.