Triple Timer Module
Timer Modes of Operation
MOTOROLA
DSP56602 User’s Manual
9-15
(TE = 0). Each time the counter matches the TCPR value, a pulse is output on the TIO pin
with the width equal to timer clock period. The pulse polarity is determined by the INV
bit. If counter wraparound occurs, the TOF bit is set, and if the TOIE is set, an overflow
interrupt is generated. The counter contents can be read at any time by reading the TCR.
Note:
After the TE bit is set, the TIO pin output value is set equal to the INV bit to
guarantee the correct first pin transition.
9.5.1.3
Mode 2—Timer, Output Toggle (Internal Clock)
This mode is selected when TC[3:0] is set to 0010. In this mode, the counter is cleared
after the TE bit is set and loaded with the TLR value on the first timer pulse derived
either from the DSP clock divided by two (CLK/2) or from the prescaled clock input.
The following timer pulses increment the counter. When the counter matches the value
of the TCPR, the TIO output pin is toggled, the TCF bit in TCSR is set, and if the TCIE bit
is set, a compare interrupt is generated. At the next timer pulse, the counter is loaded
with TLR value (if TRM is set) and the count is resumed. If TRM is cleared, the counter
continues to be incremented on each timer pulse. This process is repeated until the timer
is disabled (TE = 0). The TIO polarity is determined by the INV bit. On the first match,
the TIO output is set if the INV bit is cleared, or cleared if the INV bit is set. If counter
wraparound occurs, the TOF bit is set, and if the TOIE bit is set, an overflow interrupt is
generated. The counter contents can be read at any time by reading the TCR.
Note:
After the TE bit is set, the TIO pin output value is set equal to the INV bit to
guarantee the correct first pin transition.
9.5.1.4
Mode 3—Timer, Event Counter (External Clock)
This mode is selected when TC[3:0] is set to 0011. In this mode, the counter is cleared
after the TE bit is set and loaded with the TLR value on the first transition on the source
clock, which can be either the TIO input pin or the prescaled clock input. The following
transitions increment the counter. When the counter matches the value contained by
TCPR, the TCF bit in the TCSR is set. If the TCIE bit is set, a compare interrupt is
generated. At the next transition, the counter is loaded with TLR value if the TRM bit is
set, and the count is resumed. If the TRM bit is cleared, the counter continues to be
incremented with each transition of the source clock. This process is repeated until the
timer is disabled. The INV bit determines whether 0-to-1 transitions (the INV bit is
cleared) or 1-to-0 transitions (the INV bit is set) increment the counter. If counter
wraparound occurs, the TOF bit is set, and if the TOIE bit is set, an overflow interrupt is
generated. The counter contents can be read at any time by reading the TCR. The
external clock is internally synchronized to the internal clock and its frequency should
be lower than the DSP internal clock (CLK) divided by four.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
ARCHIVED BY FREESCALE SEMICONDUCT
OR,
INC.
2005
