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Triple Timer Module

Triple Timer Module Programming Model

 

MOTOROLA

DSP56602 User’s Manual 

9-7

 

 

9.4.1

Timer Prescaler Load Register (TPLR)

The Timer Prescaler Load Register (TPLR) is a 16-bit read/write register that controls the 
prescaler Divide Factor and the source for the prescaler input clock. The control bits are 
described in the following paragraphs.

9.4.1.1

Prescaler Preload Value (PL[13:0])—Bits 0–13 

The Prescaler Preload Value bits (PL[13:0]) contain the prescaler preload value. This 
preload value is loaded into the prescaler counter whenever either the counter reaches 
the value of 0 or the counter switches state from disabled to enabled. For PL[13:0] = N, 
the prescaler counts N + 1 source clock cycles before generating a prescaled clock pulse. 
Therefore, the prescaler Divide Factor is the preload value + 1.

The PL[13:0] bits are cleared by hardware and software reset .

9.4.1.2

Prescaler Source (PS[1:0])—Bits 14–15

The Prescaler Source (PS[1:0]) bits control the source of the prescaler clock. Table 9-1 
summarizes the functionality of the PS bits. The DSP internal clock CLK divided by two 
is selected when the PS[1:0] bits are cleared. The other combinations select one of the TIO 
pins as the source clock for the prescaler, regardless of the operating mode of the 
selected timer. 

Notes:

1.

If the prescaler source clock is external, the prescaler counter is 

incremented by the transitions on the TIO pin. The external clock is 
internally synchronized to the internal clock and its frequency should be 
lower than the DSP internal clock (CLK) divided by 4.

 2.

To ensure proper functionality, the PS[1:0] bits should be changed only 

when the prescaler counter is disabled.

The PS[1:0] bits are cleared by hardware and software reset.

Table 9-1   

PS[1:0] Bit Functionality

PS1

PS0

Prescaler Clock Source

0

0

DSP internal clock (CLK) divided by two

0

1

TIO0

1

0

TIO1

1

1

TIO2

 

   

  

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Freescale Semiconductor, Inc.

For More Information On This Product,

   Go to: www.freescale.com

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.

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ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

ARCHIVED BY FREESCALE SEMICONDUCT

OR,

 INC.

 2005

Содержание DSP56602

Страница 1: ...SECTION 9 TRIPLE TIMER MODULE Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEMICONDUCTOR INC 2005 ARCHIVED BY FREESCALE SEMICONDUCTOR INC 2005 ...

Страница 2: ... 3 9 3 TIMER ARCHITECTURE 9 4 9 4 TRIPLE TIMER MODULE PROGRAMMING MODEL 9 6 9 5 TIMER MODES OF OPERATION 9 13 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEMICONDUCTOR INC 2005 ARCHIVED BY FREESCALE SEMICONDUCTOR INC 2005 ...

Страница 3: ...TRIPLE TIMER MODULE ARCHITECTURE The triple timer module includes a 16 bit Timer Prescaler Load Register TPLR a 16 bit Timer Prescaler Count Register TPCR a 14 bit Prescaler Counter and three timers Each one of the three timers can use the Prescaler Clock as its clock source The Timer Prescaler Load Register TPLR is a 16 bit read write register that controls the Prescaler Divide Factor and the sou...

Страница 4: ...ach timer as a memory mapped peripheral occupying four 16 bit words in the X data memory space The user can use standard polled or interrupt programming techniques The programming model is shown in Figure 9 3 on page 9 6 Figure 9 1 Triple Timer Module Block Diagram Timer Prescaler Count Register GDB 16 16 TPLR 16 Timer 0 Timer 2 Timer 1 14 bit Prescaler CLK 2 TIO0 TIO1 TIO2 TPCR Timer Prescaler Lo...

Страница 5: ...imer interrupt Timer Control CLK 2 TIO Compare Register TCPR 16 16 Logic Load Register Count Register TLR Prescaled CLK TCR AA0744 16 16 9 2 16 16 16 16 16 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEMICONDUCTOR INC 2005 ARCHIVED BY FREESCALE SEMICONDUCTOR INC 2005 ...

Страница 6: ...imer Prescaler Count Register Reset Uninitialized Read Only PC7 PC6 PC4 PC3 PC2 PC1 PC0 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 TCF TOF TC1 TCPR0 X FF8D TCPR1 X FF89 TCPR2 X FF85 Timer Compare Register Reset Uninitialized Read Write Compare Register 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 TPLR X FF83 Timer Prescaler Load Register Reset 0000 Read Write PL7 PL6 PL4 PL3 PL2 PL1 PL0 11 10 9 8 7 6 5 4 3 2 ...

Страница 7: ...urce PS 1 0 bits control the source of the prescaler clock Table 9 1 summarizes the functionality of the PS bits The DSP internal clock CLK divided by two is selected when the PS 1 0 bits are cleared The other combinations select one of the TIO pins as the source clock for the prescaler regardless of the operating mode of the selected timer Notes 1 If the prescaler source clock is external the pre...

Страница 8: ... 16 bit write only register In all modes the counter is preloaded with the TLR value after the Timer Enable TE bit in the TCSR is set and a first event occurs In Timer modes if the Timer Reload Mode TRM bit is set the counter is reloaded each time after it has reached the value contained by the Timer Compare Register TCR and the new event occurs In Measurement modes if the TRM bit is set the count...

Страница 9: ... three TIO pins are tristated In order to prevent undesired spikes on the TIO pins when switching from tri state into active state external pull up or pull down resistors should be tied to the TIO pins 9 4 6 2 Timer Overflow Interrupt Enable TOIE Bit 1 The Timer Overflow Interrupt Enable TOIE bit is used to enable the timer overflow interrupts The overflow interrupt is generated after the counter ...

Страница 10: ...y synchronized to the internal clock and its frequency should be lower than the internal operating frequency divided by 4 CLK 4 Table 9 2 TC 3 0 Bit Functionality TC3 TC2 TC1 TC0 TIO Clock Mode 0 0 0 0 GPIO Internal Timer GPIO 0 0 0 1 Output Internal Timer Pulse 0 0 1 0 Output Internal Timer Toggle 0 0 1 1 Input External Event Counter 0 1 0 0 Input Internal Input Width 0 1 0 1 Input Internal Input...

Страница 11: ...The Timer Reload Mode TRM control bit determines the counter preload operation In Timer and Watchdog modes the counter is preloaded with the TLR value after the TE bit is set and a first event occurs If the TRM bit is set the counter is reloaded each time it reaches the value contained by the Timer Compare Register and the new event occurs In PWM mode the counter is reloaded each time counter wrap...

Страница 12: ...The Timer Compare Flag bit is cleared when writing a 1 into the TCF bit Writing a 0 into the TCF bit has no effect The bit is cleared also when the Timer Compare interrupt is serviced timer compare interrupt acknowledge The TCF bit is cleared by hardware and software reset the STOP instruction and also by timer disabling TE 0 Notes 1 Writing a 0 in the TOF or TCF bit can be done with the Bit Test ...

Страница 13: ...th Modulation Watchdog Table 9 3 summarizes these modes and the following paragraphs describe these modes in detail Table 9 3 Timer Mode Summary Mode Mode Description Mode Type TC 3 0 0 Timer Mode No Output Internal Clock Timer 0000 1 Timer Mode Output Pulse Enable Internal Clock Timer 0001 2 Timer Mode Output Toggle Enable Internal Clock Timer 0010 3 Timer Mode Output Toggle Enable External Clock...

Страница 14: ...he TCR 9 5 1 2 Mode 1 Timer Output Pulse Internal Clock This mode is selected when TC 3 0 is set to 0001 In this mode the counter is cleared after the TE bit is set and loaded with the TLR value on the first timer pulse derived either from the DSP clock divided by two CLK 2 or from the prescaled clock input The following timer pulses increment the counter When the counter matches the value contain...

Страница 15: ...F bit is set and if the TOIE bit is set an overflow interrupt is generated The counter contents can be read at any time by reading the TCR Note After the TE bit is set the TIO pin output value is set equal to the INV bit to guarantee the correct first pin transition 9 5 1 4 Mode 3 Timer Event Counter External Clock This mode is selected when TC 3 0 is set to 0011 In this mode the counter is cleare...

Страница 16: ...OF bit is set If the TOIE bit is set an overflow interrupt is generated In this mode TIO acts as a gating signal for the internal timer clock The INV bit determines whether the counting is enabled when TIO is low the INV bit is set or TIO is high the INV bit is cleared 9 5 2 2 Mode 5 Period Measurement The Period Measurement mode is selected when TC 3 0 is set to 0101 In this mode the counter is c...

Страница 17: ...tion mode Output Toggle Enable mode is selected when TC 3 0 is set to 0111 In this mode the counter is cleared after the TE bit is set and loaded with the TLR value on the first timer pulse derived either from the DSP clock divided by two CLK 2 or from the prescaled clock input The following timer pulses increment the counter When the counter matches the value of the TCPR the TIO output pin is tog...

Страница 18: ...the TCR Note In this mode the internal hardware preserves the TIO value and direction for an additional 2 5 internal clock cycles after reset was activated This ensures a valid length reset when the TIO is used as input to the RESET pin 9 5 4 2 Mode 10 Watchdog Output Toggle Internal Clock The Watchdog Mode Output Toggle Enable mode is selected when TC 3 0 is set to 1010 In this mode the counter i...

Страница 19: ...ring the execution of the WAIT instruction Thus timer activity continues undisturbed On reaching the final event if the timer interrupt is enabled an interrupt is generated and the processor leaves the Wait state and services the interrupt The timer clocks are disabled during the execution of the STOP instruction Thus timer activity is stopped In Stop mode the TIO pins are electrically disconnecte...

Страница 20: ...Timer Module Timer Modes of Operation Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ARCHIVED BY FREESCALE SEMICONDUCTOR INC 2005 ARCHIVED BY FREESCALE SEMICONDUCTOR INC 2005 ...

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