Chapter 7. Public Key Execution Unit
7-3
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Operational Registers
7.1.3 Status Register (PKSR)
The Status Register contains bits that give information about the state of the PKEU. If an
error occurs during normal operation, a bit in the PKSR will be set to 1. After a GO is issued
to the PKCR, the next jump to location 0 will cause a bit in the Status Register to be set,
followed by an interrupt on IRQ if interrupts are enabled.
The PKSR is effectively a read-only register. Its contents cannot be directly modified by the
host processor except to be reset, which occurs when the host processor performs a write
to the PKSR, regardless of the data value. Note that the host may indirectly affect the
contents of the PKSR, such as when GO is asserted.
Figure 7-2 shows the PKEU status register and Table 7-3 describes this register’s fields.
9
R
p
R
n
For a description of R
p
R
n
see Section 7.5.3, “RpRN mod P Calculation.”
0 R
2
mod N enabled
1 R
p
R
n
mod P enabled
10
RST
The RST bit is a software reset signal. When activated, the PKEU will reset immediately. All
registers revert to their initial state, and the Program Counter (PC) will jump to 0. Instruction
execution will halt, and any pending interrupt will be deactivated. All memories (A, B, and N) will
indirectly be reset since this signal causes the “clear all” routine to be executed.
0 normal processing
1 reset the PKEU
11
IE
The IE bit represents the Interrupt Enable flag. When set to 1, the IRQ signal is enabled, thus when
an interrupt occurs, the IRQ signal will be activated. When the IE bit is set to 0, all interrupts are
disabled, and the IRQ output pin will be held inactive, i.e. 0. The IE bit acts as the global interrupt
enable.
Note that this does not affect the SR[IRQ] bit. That bit is set regardless of IE.
0 interrupts disabled
1 interrupts enabled
12
GO
The GO bit initiates the execution of the routine pointed to by the Program Counter (PC). This is
accomplished by fetching the instruction addressed by the PC and to keep executing instructions
until a jump to location 0 is encountered which tells the PKEU to stop executing. It is important to
realize that once the PKEU is “going”, the host has limited access to the PKEU internal memory
space. Specifically, reads and writes to the RAMs are ignored during this state and all other
locations must be referenced with extreme caution. Under normal circumstances, only the Status
Register and EXP(k) should be actively referenced during this mode.
0 rest condition
1 execute instructions without stopping
13
ECC
The ECC bit signifies that one of the ECC-related routines will be executed. Conversely, by not
setting this bit, the PKEU will be configured to correctly execute RSA-related routines.
0 RSA processing enabled
1 ECC processing enabled
14–15
—
Reserved, should be cleared.
Table 7-2. PKCR Field Descriptions (Continued)
Bits
Name
Description
F
re
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sc
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le
S
e
m
ic
o
n
d
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c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
..
F
re
e
sc
a
le
S
e
m
ic
o
n
d
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c
to
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I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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.
..
