background image

The

drum

output

circuit

consists

of

latches U12 and U13

,

buffers

U6 and

U16

.

pulse

t

i

me

r

U1

4

A

and

R50

and

d

r

um mode

latches U15B.

Th

e drum outp

u

t

latches can

operate in eit

h

er a pulse

mode or

a latch

mode

depending on the status

of flip flop

U15B.

I

n

the latch

m

ode

.

t

h

e

output

of

U15B

i

s

"

0

",

disab

l

ing reset circuit U1

4

B.

Data f

r

om the buffered data bus

is latched

by U13 and U12

D

O

=

DR

UM

TRIGGER

1.

D7

=

DRU

M

T

R

IGGER 8

.

The output

s f

rom

U

13

and U12 are

buffered

by U6 and U16

and sent to t

h

e Drum Trigger

outputs 1 through 8

.

W

hen

Pin

13 of UlsB

is

high.

the drum output

operates

i

n

a

pulse mode

. W

hene

v

er a

"1"

is

w

ritten to

a

n

y

output

of

U13

o

r

U12

,

d

iodes

CRS

through CR12 coup

l

e

t

hat "1

"

to

the

input

of

U1

4

A.

U14

A charges

C26

through

RSO

.

When the

v

oltage on

C26 equals 2.5

v

olts,

the output of U1

4

B goes negative

resetting

latc

h

es

U12 and

U

13 bac

k

to z

e

ro

.

C26 and

R50

.

a

drum pulse

w

i

d

t

h

tri

m,

sets the

time

constant

and

t

hereb

y

adjusts

the

pulse

w

idt

h

.

The

CLO

CK

I

N

(CI)

and

CLOCK

IN DISABLE

(CID) circuits consist

o

f

U1

,

U3A

.

U2A,

UIO and USB.

T

he C

I

and CID circ

u

its

allo

w

e

x

ter

n

al

inst

rum

ents

,

such

as

drum

machi

n

es

.

to be used as a

time

base

for

the

So

n

g

Producer

.

When

enabled,

clock

pu

l

ses

on

CI

generate

a

non-maskable

i

n

terrupt

that

is

fed

back

to

the

Commodore 6

4

an

d

used as

a

timing signal.

The CID

.

.

in

conju

n

c

t

ion

w

ith

latch USB.

can be used

t

o

in

h

ibit the actio

n

of

CI

.

Either

a

"

1" o

n U

SB

or a "0" on

CID will

i

nh

i

bit

U2A from pas

s

i

n

g the

clock signal

to

UIOD

,

thereb

y

disabling

it.

If

U2A

gene

r

ates

a

n

i

n

ter

r

upt

,

the

signal

is

i

nver

t

ed

b

y

U

I

OD

and

aga

i

n

b

y

U10C and

se

n

t

t

o

the

NMI

l

i

n

e.

Since

i

t

is

impe

ra

ti

v

e

th

a

t n

o

n

-

m

as

k

a

b

le

interrupts do

no

t

occur

unti

l

the

sof

tw

are

sets

the

Commodore

u

p

to

re

c

ei

v

e

them,

the

A

sectio

n

of

U

S

is

used

to

i

nhibit

the

interrupt

s

u

pon

po

w

er

up

.

This

is

d

escr

i

bed

ful

l

y

in

th

e

IN

TER

R

UPT

DISABLE

section

.

U4

p

r

o

v

i

d

es

both

a

CL

O

C

K

O

UT

(CO)

an

d

CLO

C

K

O

UT

D

I

S

A

B

LE

(COD

)

fo

r

d

r

iving

e

x

te

rnal

d

rum

m

ac

hin

es.

Wh

e

n

e

v

er a

"1" is

wr

itten

t

o

B

DI

of U

4

A

,

U4A

c

h

arges

C9

throug

h

R

16

a

n

d

R

17

.

Wh

e

n

t

h

e

v

o

l

tage on

C9

e

x

ceeds

th

e

thr

es

ho

l

d v

o

l

tage

on

the

reset

i

n

put

, U4

A

r

e

sets t

o

"0" producing a

p

u

l

se. R16

.

R17 a

n

d C9

se

t

t

he pulse

w

idth

to

665

m

icrose

con

d

s

.

Thi

s is

bu

ffered

b

y

U6B an

d

fe

d t

o

C

O. T

h

e

C

O

D

is

latc

h

ed

b

y

U4

B fro

m BDO.

U

7 is

a

t

r

i

-s

t

a

t

e

bu

ff

er

u

se

d

F

oot

swi

tc

h

I

N

1

a

nd

2

t

o

t

h

e

W

he

n

e

v

e

r

me

mo

r

y

l

o

cati

o

n

D

EOC

rea

d

.

th

e

data

on

Foo

t

s

w

itch I

N

tra

n

sfe

r

re

d

t

o th

e

d

at

a

bu

s

on

6.

"0

"

=

s

w

itc

h d

epres

s

e

d.

Al

l

bi

t

s

ar

e

u

n

u

se

d

an

d

se

t

resistors

R3

0

t

h

r

oug

h

R3

7

.

to

feed

da

t

a

bus

.

(5

68

44

)

i

s

1

a

nd

2

is

b

i

t

s 7 a

n

d

othe

r

d

ata

to

"

1

"

b

y

To

r

eceive in

f

o

r

mat

i

on.

t

h

e

se

ri

al

d

at

a

stream

is

fed to

M

IDI IN t

h

ro

u

gh

J

2

0

.

I

t

is

opt

i

ca

l

ly

isolated

by

U2

2

an

d

fed

t

h

rough

buf

f

er U21D

to

t

h

e recei

v

e

da

t

a

i

n

put o

n

U

1

7

.

W

he

n

the recei

v

e

d

a

ta

buf

f

er

rece

i

ves

al

l

8

da

t

a

bits. a

n

i

nte

r

rupt

request

is

generated

wh

ich is

fe

d

t

o the

computer

through UIO

and a

"1"

i

s

set

in

bit

7

of it

'

s

o

w

n

status register

.

The

Commodore

64 reads the status register

of

each

A

CIA and when it fin

d

s a "1

"

i

n

bit

7

of th~ status data registe

r,

it

th

e

n

reads

the

rece

iv

e

data.

Then

it

is

r

eady

to

recei

v

e t

h

e ne

x

t se

r

ial data

tr

a

n

sm

i

ssio

n.

The recei

v

e data stream

i

s also

fed

t

o U21

and out

the

M

IDI

TH

R

OUGH jac

k

to

dr

i

ve

ot

h

er MIDI based instrume

n

t

s

.

S

i

nce

U17 through

U20 all

t

ransmit in the

same

fash

i

on

.

w

e'll

only

loo

k

at

U

1

7

.

Whene

v

er the computer

w

ants to se

n

d a

M

IDI

command

.

it first

w

rites into the transmit

data register of

U17

.

When the

data

word

is

latched.

U1

7

adds

1 start

bit

,

then

feeds

the

data

out in a serial stream to

output

"W

"

.

A

t the end of the

8 data bits.

it

adds

one

stop bit

.

W

hen

the

w

ord

is

successfu

ly

t

r

ansmitted, U17

ge

n

erates

an

interrupt

.

telling the microprocessor that

it is ready to

r

eceive the next

word

for

transmission

.

U18, U

1

9 and U20

operate

i

n

e

x

actly the same matter as

U

17

.

It

i

s

i

mpe

r

ati

v

e

t

h

at

no

interrupts

,

either

inter

r

upt requests or

non-maskable

interrupts

are

generated

by

the

Song

Producer

before

the

sof

t

ware

has

programmed

the

Commodore

6

4

to

handle

them

.

Therefore

,

USA

i

s

conf

i

gured

to

disable

both

t

he

NM

I

v

ia

UI

OC and IRQ

v

ia

UIOB from

t

h

e Song Producer upo

n

power

u

p.

W

hen

po

w

er

i

s

s

u

pplied

t

o

the

Song

Producer

,

C

l

8

hold

s

t

he

reset pin of USA

high

fo

r

appro

x

imate

l

y

1

seco

n

d.

This

causes t

h

e "Q" outpu

t t

o go

lo

w

, disabl

i

ng

U

I

O

w

hich

disables both

inter

r

upt

lines

.

T

o

enable

bot

h.

a "1

"

is

w

ritten to USA

w

hich

enables U

I

OB and

C.

Therefo

r

e

,

the

clock

i

nput

can

then

generate

a

N

O

N

-MASKABLE I

N

TERRUPT

(N

M

I)

or the ACI

A'

s

can generate an INTERRUPT REQUEST

(IRQ

)

.

M

IDI stands for

Mu

sical Ins

t

r

u

me

n

t

Digital

Interface.

M

IDI

is

a

d

igital

serial

communicaion

c

h

annel

(sim

i

lar

to

RS2

3

2)

that

allo

w

s similar

l

y equipped inst

r

uments

to

communicate

w

ith

eac

h

othe

r

at

th

e

lo

we

st

le

v

e

l

the

y

b

oth

u

n

d

e

r

sta

n

d

. In t

he

case of the So

n

g Pro

du

cer

,

M

I

D

I allo

w

s t

h

e

C

o

m

m

odore

6

4

to

commun

i

cate

and co

n

trol

s

y

nthes

iz

e

rs

and

d

ru

m

mac

h

ines

.

It

communic

a

te

s w

ith 1

0

bit

w

ords

co

nsi

sting

of

one

star

t

bi

t

, 8 data

bits a

nd

1

s

top

bit at a

31.25

k

Hz

b

it rate

.

T

o

re

d

uce

ground

l

oops

,

th

e

M

I

D

I

i

nput i

s

opt

i

cal

ly

isolate

d.

T

h

e

M

I

D

I

serial

d

at

a

s

tr

eam

i

s

b

oth

transmitted

a

n

d

r

e

cei

v

ed

b

y

a

s

y

nchronous

com

m

un

i

cat

i

o

n

i

n

terface

adaptors

(

ACIA

)

U1

7

t

hr

ough

U20

.

T

he

A

CI

A'

s

are

prog

r

am

m

able

de

vi

ces

wh

ic

h

can

selec

t

d

iff

eren

t d

a

t

a

rat

e

s

,

w

ord siz

es

a

n

d ot

her

p

a

r

ame

t

e

r

s

.

Th

e

sy

s

t

e

m

cloc

k 02 i

s d

iv

ided

b

y

U15A to 500

kHz. E

ach of

t

h

e

A

CI

A

'

s is

p

r

ogramme

d

t

o d

i

v

ide this c

l

oc

k

by

1

6

to

g

e

nerate

t

he 3

1.

25

kH

z ti

mi

ng s

i

g

n

a

l

s

u

s~d

for

M

IDI tr

an

s

mi

ssi

on o

r rec

e

p

tion

.

www.bleeps-and-peeps.com

Содержание Song Producer

Страница 1: ...a Waalhaven Zuidzijde 48 3088 H J Rotterdam The Netherlands These drawings and specifications are the property of Moog Electronics Inc and shall not be reproduced or copied in whole or in part as the basisfor manufacture or saleof the ite COPYRIGHT 1985 MOOG ELECTRONICS INC www bleeps and peeps com ...

Страница 2: ...sabled LSTTL cortpatible Logic Output rive Pu se dd 0 tp ts he se_ected Active High Trigger LSTTL cortpatible 200 milliseconds nominal Software selectable for latched or pulsed outputs MEMORY MAP RESS HEX c MAL READ WRITE FUNCTION WRITE U17 IlWIl CONTROL REGISTER READ Ul7 IIWll STATUS DATA REGISTER WRITE U17 WI TRANSMIT DATA REGISTER READ U17 WI RECEIVE DATA REGISTER f RITE U18 XII CR READ U18 XII...

Страница 3: ... 2 Address Decoder 3 Control Latch Driver 4 Drum Output Circuit 5 Clock In and Clock In Disable Circuit 6 Clock Out and Clock OUt Disable Circuit 7 Footswitch Inputs NOTE ALL ADDRESSES ARE IN HEX AND ARE FOLLOWED PARENTHETICALLY BY THEIR DECIMAL EQUIVALENT 8 MIDI Input and Output Circuits 9 Interrupt Disable Circuit The bus buffers consist of U8 and U9 U8 is a bi directional bus transceiver connec...

Страница 4: ...y isolated by U22 and fed through buffer U21D to the receive data input on U17 When the receive data buffer receives all 8 data bits an interrupt request is generated which is fed to the computer through UIO and a 1 is set in bit 7 of it s own status register The Commodore 64 reads the status register of each ACIA and when it finds a 1 in bit 7 of th status data register it then reads the receive ...

Страница 5: ...n ASSEMBLY 996 046270 001 e __ ill TOP VIEW www bleeps and peeps com ...

Страница 6: ... KS I c J CJ J15 c J JIS nl R38 X 35 3 R8 e J 33 R8 R32 R82 c J c R31 B3 JIJ C13 R1 c J R14 c J RlO c J J IS THRU R83 R84 i C c J W IN o J www bleeps and peeps com ...

Страница 7: ... I c JJ o C Ci c m r C260 www bleeps and peeps com ...

Страница 8: ... J www bleeps and peeps com ...

Страница 9: ...50 7 1 0 7 170 180 19 0 200 210 I I I I 70 50 EO yO X 0 wO V 0 uO TO 50 RO I I 00 I I 40 I I L DRUM TRIGGER LATCH BD SV R20 22K G U2 5 1 4 74 LsjlID S CONTROL LATCH CLOCK yV R l8 10K R28 IK CI8 IO 50V 20 lo C G4 EXPANSION PORT I I 1 _ www bleeps and peeps com ...

Страница 10: ...M R57 I BOO d RDDlrA 6 5 10K r2 Kj 54 U21 C 7 1 3 10K C32 NC 3 OUT I Uh412 R55 I 15V BD7 R30 5v 11 1 1V 5V NC I I 10K j 41 1 1 C33 5V rR86 U R56 BD6 R I 9 OCDC CSal H R87 220 JIG LM393 10K BD5 R32 SD7 IS C52 CSI 1 10K R 8 4 BD4 R 2 BOG If RS II 6Adl 4r IG 2 0 4 BD5 17 u20 I k S SD ReA BD4 I HD6350 E 14 2 U21 74LS3G5 r2 I1J BD2 tjD3 15 R3 BD2 29 ACIA TC t NC 3 OUT SOl pj SOl 21 RC 3 5V NC I BDQ R07...

Страница 11: ...D SCREW BLACK 4 14 X 1 4 POP RIVETS DOME HEAD 1 8 X 328 INTERCONNECT PC BOARD BREAK AWAY 26 PIN NOVO CONNECTOR RIGHT ANGLE HEADER CAPACITOR 1 uf CERAMIC MONOLITHIC EJECTOR LATCH NOVO CONNECTOR RIBBON CABLE ASSEMBLY 6 COMPLETE FLAT CABLE 26 CONDUCTOR 26 PIN NOVO CONNECTOR RECEPTACLE 26 PIN NOVO CONNECTOR RECEPTACLE LM393 74LSOO 74LS02 4013 4013 74LS365A CD4503 74LS245 74LS365A 74LS26 74LS138 40174B...

Страница 12: ...001 5 1M 1 41015 CARBON FILM 470 47 pf CERAMIC TUBULAR R48 852 312103 001 10K 1 41015 CARBON FILM 470 47 pf CERAMIC TUBULAR R49 852 312103 001 10K 1 41015 C R30N FILM RSO 925 042526 005 lOOK LIN AR CER IE l TRIM DRUM PULSE IOTH DIODES RS1 852 312102 001 lK 1 41015 CARBON FILM RS2 852 312202 001 2K 1 41015 CARBON FILM R53 852 312515 001 5 1M 1 41015 CARBON FILM R54 852 312103 001 10K 1 41015 CARBON...

Страница 13: ...L1TY OR FITNESS FOR A PARTICU POSE A E HEREBY DISCLAIMED FROM THIS WARRANTY IN CLUDING BUT NOT LIMITED TO ANY INTERRUPTION OF SERVICE L SS OF BUSI ESS A TICIPATORY PROFITS OR CONSEQUENTIAL DAMAGES OR INCIDENTAL DAMAGES RESULTING FROM THE USE OPE COMPUTER MEDIA DISCLAIMER THIS WARRANTY SHALL NOT APPLY I F THE COMPUTER MEDIA IZED SERVICE OR BY OTHER CAUSES UNRELATED TO DEFECTIVE MOOG MAKES NO WARRAN...

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