483
FX
3U
/FX
3UC
Series Programmable Controllers
Programming Manual - Basic & Applied Instruction Edition
18 Floating Point – FNC110 to FNC139
18.11 FNC123 – EDIV / Floating Point Division
11
FN
C30-
FN
C39
R
o
ta
tion and
Sh
ift
12
FNC
4
0
-FNC49
D
a
ta
Op
e
ra
tio
n
13
FNC5
0
-FNC5
9
H
igh Speed
Pr
ocessi
ng
14
FM
C6
0
-F
NC6
9
H
and
y
In
st
ru
cti
o
n
15
FNC7
0
-FNC7
9
Ex
te
rn
a
l F
X
I
/O
D
evi
ce
16
FNC8
0
-FNC8
9
Ext
e
rnal
FX
D
evi
ce
17
F
N
C1
00
-F
NC
10
9
Da
ta
Tr
ansf
e
r 2
18
FN
C
110-FN
C
13
9
Fl
oat
ing P
o
in
t
19
FN
C
140-FN
C
149
Da
ta
O
per
at
io
n
2
20
FN
C
15
0-F
N
C
159
P
o
si
tioni
ng
C
ont
ro
l
18.11 FNC123 – EDIV / Floating Point Division
Outline
This instruction executes division of two binary floating point.
→
For program examples of floating point operations, refer to Section 12.10.
→
For handling of floating point, refer to Subsection 5.1.3.
→
For flag operations, refer to Subsection 6.5.2.
1. Instruction format
2. Set data
*1.
When a constant (K or H) is specified, it is automatically converted into binary floating point (real
number) when the instruction is executed.
3. Applicable devices
Explanation of function and operation
1. 32-bit operation (DEDIV and DESDIVP)
Binary floating point data [
+1,
] is divided by binary floating point data [
+1,
], and the
division result in the binary floating point format is transferred to [
+1,
].
When a constant (K or H) is specified as [
+1,
] or [
+1,
], it is automatically converted
into binary floating point.
Operand Type
Description
Data Type
Word device number storing binary floating point data used in division
Real number
(binary)
*1
Word device number storing binary floating point data used in division
Data register number storing the division result
Oper-
and
Type
Bit Devices
Word Devices
Others
System User
Digit Specification
System User
Special
Unit
Index
Con-
stant
Real
Number
Charac-
ter String
Pointer
X Y M T C S D
.b KnX KnY KnM KnS
T
C
D
R U
\G
V
Z Modify K
H
E
"
"
P
3 3
3
3
3 3
3
3 3
3
3
3 3
3
3 3
3
3
P
FNC 123
EDIV
D
−
Mnemonic
Operation Condition
16-bit Instruction
DEDIV
DEDIVP
Mnemonic
Operation Condition
32-bit Instruction
13 steps
Continuous
Operation
Pulse (Single)
Operation
S
1
S
2
D
S
1
S
2
D
S
1
S
1
S
2
S
2
D
D
Command
input
FNC123
DEDIV
S
1
S
2
D
[ +1, ]
÷
[ +1, ]
→
[ +1, ]
Binary floating point
Binary floating point
Binary floating point
S
1
S
1
S
2
S
2
D
D
Dividend
Divisor
S
1
S
1
S
2
S
2
Command
input
FNC123
DEDIV
K100
S
1
D
[ +1, ]
÷
[ K100 ]
→
[ +1, ]
Binary floating point
Automatically
converted into binary
floating point
Binary floating point
S
1
S
1
D
D
Dividend
Divisor
Содержание FX3U Series
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