Mitsubishi CV-0MW3R45, Руководство по обслуживанию

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DQ9
U-com_24pin
U-com_49pin
U-com_52pin
VDD
GND
NC CE
GND
VOUT
AXR0[4]
AXR0[3]
AXR0[0]
GP2[6]
GND
JTAG
GP2[2]
EMA_D[11]
PCM1690
PCM1753
EMA_OE
NC
NC
OPEN
BYTE
VSS
GND
NC
OE
BOOT[3]
AXR0[2]
max3A
EMA_A[10]
EMA_WE
EMA_A[9]
EMA_A[8]
EMA_A[7]
EMA_A[6]
AXR1[4]
EMA_A[12]
EMA_CS[2]
EMA_D[1]
48kHz*512=24.576MHz
BOOT MODE:NOR
BOOT[7]
GND
EMA_A[11]
OPEN
NC
DQ1
Write protect
A7
0
AXR0[1]
D3.3V
0
EMA_D[0]
EMA_D[5]
X
0
WP
A1
A6
A16
DQ5
CE
A0
DQ10
A9
A19
A17
A2
EMA_BA[1]
DQ4
TMS
TRST
TCK
GND
NC
DQ8
DQ0
A10
A15
A14
DQ2
GND
TDO
EMA_D[3]
EMA_D[4]
AXR1[3]
GP2[4]
EMA_A[2]
EMA_D[7]
EMA_D[8]
EMA_D[10]
EMA_D[13]
EMA_D[14]
EMA_D[2]
EMA_D[6]
EMA_D[9]
EMA_D[12]
EMA_D[15]
VSS
A5
BOOT[1]
1
DQ3
DQ15
DQ7
DQ6
DQ13 A8
A11
BOOT[2]
BOOT[0]
EMA_A[0]
GP2[0]
GP2[1]
DQ12
OUT
NC
DQ11
EMA_A[5]
RESETOUT
EMA_A[3]
EMA_A[4]
AXR1[2]
OPEN
OPEN
EMU0
PU
NC
AXR1[8]
AXR1[7]
GP2[8]
A12
EMA_A[1]
DQ14
A13
DA810
NC
VDD
VCC
WE
NC
RESET
RY/BY
A18
A4
A3
TCK
DSP1.2V
PCM1690
DSP3.3V
DSP1.2V
TDI
(CH) 18p
24.576M
R7
X
0
1M
OSCOUT
OSCIN
AFSR2/
ACLKR2/
AHCLKR2/
USB1_DP
USB1_DM
USB0_DRVVBUS/
USB0_VBUS
USB0_ID
AFSR1/
AMUTE1/
N2
GPIO4[4]/
GPIO4[3]/
GPIO4[2]/
C7
T1
100
R7T1
4
DSP_DIST
DSP_CHECK
P5
RTC_XO
ACLKR1/
AD_DATA7
TC7SH08FU
4
R779
R780 EMB_RAS*
L7114
(CH)
C7
J4
R7J4G 47k
R7J4A
R70R1
10k
47k
R856
R859
47k
R78N4
22k
10k
R77H1
FB
M
H
3216H
M
501N
T
C
745
0.
1u
C
736
2200p
10k
22u
0.
1u
M12
DVDD
DVDD
0.01u
25V
10V
E1
RTC_VSS
RTC_CVDD
2200p
2200p
0.
1u
6.3V
(X5R)
C714
6.3V
C715
(CH)
(CH)
2200p
C707
C7G
1
C7
G
2
BLM31PG500SN1L
L753
(2125)
0.22
R8301
68p
R7A1
DA_DATA1
180
M4
BOOT[6]/
L7A3
DA_DATA3
0.
1u
VSS
0 L7R6
0
0
0
0
L7R3
L7P3
0
0 L7N4
BOOT[7]/
BOOT[8]/
BOOT[9]/
0
EMB_CAS*
2
0
R784
G13
10
13
C7306
(B
)
4
A14
EMB_D[26]
UHPI_HDS1*/
R7A
7
1k
R7
A
6
1k
M14
G3
N11
EMB_D[22]
EMB_D[24]
EMB_D[25]
F14
22
22
R747
3
3
22
22
R750
F15
EMB_D[31]
UHPI_HD[1]/
UHPI_HDS2*/
R8
P11
47
R
788
J5
R6
UART2_TXD
R7849
100
R7874
BOOT[5]/
BOOT[4]/
100
RTCK/
P10
GPIO1[7]/
EMB_D[4]/
A12
0
3
T6
N5
C5
D6
L14
L15
8
12
9
C
765
11
10
13
15
14
(B)
C7303
82
R730
82
R732
82
R733
82
R734
82
R735
82
1000p (CH)
C7304
10
R758
EMB_D[5]/
7
R7306
R783
0
K3
GPIO1[5]/
GPIO1[9]/
GPIO1[11]/
GPIO1[12]/
EMB_D[2]/
EMB_D[0]/
EMB_WE_DQM[3]*
EMB_D[15]/
EMB_D[14]/
EMB_D[13]/
EMB_D[11]/
GPIO1[8]/
DSP_RESET
47
47
P3
EMU[0]/
K1
J4
F4
D2
B3
R787
T7
R786
L2
L1
R7ND3
R7ND1
N9
T11
UHPI_HD[12]/
UHPI_HD[13]/
UHPI_HD[14]/
UHPI_HD[15]/
R7859
R5
AXR0[9]/
1
T5
UHPI_HCS*/
UHPI_HINT*/
H1
R7X2
E4
VSS
VSS
L7
(B
)
10V
6
52559-1452
47 R7E0
47
R7C9 47
R791
R792 47
R793
47
R795
47
R797
47
47
47
R7A8 47
47
R7B0 47
47
R7B2
0
TMS320D810K003BZKBT
DSP_NOR_DATALINE(15..0)
UHPI_HD[7]/
UHPI_HD[6]/
UHPI_HD[5]/
UHPI_HD[4]/
EMB_D[29]
P12
R15
R13
P13
P15
56
R7B5
56
R701
R703
R704
33
33
33
33
33
33
33
56
R7B3 56
56
R7B6
R7B7
R7B8 56
R7B9 56
R7C0 56
56
56
56
R7C5 56
R7C6
56
R7C8
T13
R14
P16
N12
N15
T14
N14
M16
UHPI_HHWIL/
R9
14
9
8
7
6
12
11
R744
22
R742
R741 22
R740
22
R737 22
82
R725
1
0.
1u
82
1000p
(B)
C7308
0.1u
B9
C9
5
0
11
10
9
4
8
9
(CH)
2
7
6
EMB_D[17]
EMB_D[18]
10
R753
AFSR0/
A4 N4
P6
P4
H2
N1
P9
D5
K14
AHCLKR1/
H3
J3
J2
TDI
D10
C10
H15
N6
T8
N13
M15
P14
N16
J14
P8
N7
J16
C16
H13
F2
B8
A9
D11
D16
D15
D14
D13
H16
C4
C7
B7
A13
R3
E2
D8
E13
L16
E15
E14
C12
R7
B11
B10
C14
R10
N10
E16
M13
EMB_D[3]/
A8
C13
K15
A10
F16
C6
TCK
D3
R12
TDO
UHPI_HD[3]/
UHPI_HD[9]/
T10
C8
A6
B4
P7
N8
R11
EMB_CLK/
J1
G16
EMB_A[3]/
EMB_A[4]/
EMB_A[6]/
EMB_A[7]/
EMB_A[8]/
EMB_BA[1]/ UHPI_HCNTL1/
UHPI_HCNTL0/
EMB_A[2]/
EMB_D[30]
D12
B5
D9
H14
K2
AXR0[10]/
B14
EMB_D[20]
EMB_D[19]
10
R754
10
R756
10
R776 10
10
R751
R
789
DSP_ENA
DSP_SIMO
DSP_SOMI
6
21
0.
1u
G1
H4
H5
C1
C754
E10
VSS
VSS
0.
1u
36
8
6
3
33
46
C
709
C
705
0.
1u
5
D9D33
L12
CVDD
VSS
K10
K11
H6
H12
H8
J8
VSS
A15
A16
GND7
1k
3
CVDD
F7
10V
9
12
2
(B
)
1u
1
R72A
7
L5
M11
J6
12
1
2
3
14
13
12
85
DA_MCLK
DA_BCLK
open
(B
)
R782
0 0
10k
0
1
2
5
CVDD
2
0
G7
VSS
T15
DVDD
K8
A2
L9
K9
J9
H9
F9
L8
G8
L6
K7
J7
H7
G6
F6
M6
E11
E7
E6
L11
F12
F5
VSS
DVDD
VSS
VSS
F11
DVDD
6
3
1
15
12
11
8
9
10
6
7
5
4
0
1
2
3
5
4
10k
C
704
10u
1
5
6
1
2
3
13
M7
10u
H10
22u
C
756
3
0
1
3
2
6
1
0
9
8
7
5
4
11
0 4
7
R7WP0
DVDD
DVDD
DVDD
7
14
B1
3
10k
K6
2
22u
6.
3V
1k
E12
CVDD
47
44
43
41
34
30
29
28
27
26
25
1
5
6
7
12
13
14
15
16
17
18
19
20
22
23
P200
R7X3
DA_DATA_3
100
47k
11
DA_LRCK_OUT
DA_BCLK_OUT
DA_MCLK_OUT
(1608)
0.
1u
R770
P1
C15
14
R759 10
J13
A7
AFSX2/
0.
1u
R736
A11
C11
EMB_D[23]
R748
R743
L3
0
0
0
0
0
0
0
9
8
7
6
5
4
3
0
1
2
24
open
12
10
11
3
2
1
0
1
2
4
3
5
10
13
15
TMS
10
*
A5
47
R
790
R7C1
R7C3
31
32
R716
R715
8
33
35
8
10k
1000p
(CH)
R739
22
G14
7
22
2
0
1
7
0
0
*
0
R781
10
10
R777
0
R778
B13
47
47
47
R796
47
T4
L7J3
1804DATA
0
DA_DATA_1
DA_DATA_2
R7L4
GPIO5[10]/
6.
3V
L754
56
F10
0
0
11
C7305
22
R749
22
22
10
F13
K16
K13
R752
R771
R773
R775 10
R785
M2
GPIO5[11]/
R7A0
AD_LRCK
(1608)
open
DA_LRCK
R7D0
R7D1
330 R7D2
330
330
GPIO4[8]/
GPIO4[6]/
P2
R2
T3
M3
ACLKX2/
D4
L7A4
L7J2
47k
R7AM0
M1
L7J1
UART2_RXD
GPIO4[9](PD_MICAD) RTC_XI
L7R5
USB0_DP
USB0_DM
C7X1
50V 18p
IC9D33
6.3V
VSS
T1
0.
1u
A3
DSP_SIMO
R874
DSP_SCS
R70B7
R4
VSS
VSS
EMB_D[28]
GPIO1[14]/
R7
J9
R7
J8
47k
R7T9 T9
EMB_A[9]/
EMB_A[5]/
EMB_D[27]
EMB_D[21]
EMB_D[12]/
180
0
B15
B12
1k
L7T5
L7P6
50V
(CH)
VSS
VSS
A1
C716
12
33
40
42
33
15
33
33
33
39
9
11
C
764
E5
0.
1u
C
746
C
743
38
R7ND2
47
R774
R772
J15
1k
EMB_CS[0]*
L13
L4
DA_DATA2
180
AD_BCLK
AD_MCLK
180
180
180
68p
CH
R7
J7
68p
CH CH
R7
J5
K4
L7J4
47
R799
10
22p
0.
1u
DVDD
BLM31PG500SN1L
OSC_IN
D7
DA_DATA4
AD_BCLK_OUT
AD_MCLK_OUT
R
G
070
EMB_A[10]/
EMB_A[11]/
EMB_A[12]/
EMB_BA[0]/
4
R705
6
33
UHPI_HD[8]/
G15
EMB_D[16]
RESET*
GPIO4[5]/
GPIO4[7]/
0
AFSX0/
0
F1
R7X
1
X7X1
G4
GPIO3[2](PD_TELAD)
AXR2[1]
AXR2[0]
OSCVSS
0
C7X2
0.
1u
C
703
0.
1u
2200p
100u
CVDD
CVDD
CVDD
CVDD
G11
C713
G10
C
708
10u
C
744
VSS
VSS
G2
C750
E9
(B
)
2200p
6.3V
C
719
2 4 1
6 5 7
3
PLTD3
SD01123-21
8
DSP_GND1
0.1u
open
(1608)
AMUTE2/
AXR2[2]/
L7J0
AD_DATA8
10
R757
10
R755
EMB_A[0]/
EMB_A[1]/
R7B4
0.
1u
3
FBMH3225HM601NT
(1/
10W
)
16V 10u
33
37
10
0
10u
D6A2
10V
0.1u
3
5 (X5R)
6.3V
100u
C851
VSS
C6W2
open
(1/10W)
C
738
C753
1000p
C2
L752
J11
J10
CVDD
H11
C717
C721
C3
T2
DSP_SOMI
DSP_SCLK
DSP_SCLK
DSP_SCS
DSP_DIST
100
R7856
2200p C
740
DVDD
DVDD
DVDD
G12
K5
M5
M8
0.
1u
0.
1u
C
726
C826
22u
6.3V
1
1
C
9373
C9
D3
4
11
4
R70B1
R702
G5
E8
C
728
0.
1u
C
733
2200p
C731
USB0_VSSA
F3
DVDD
B16
VSS
(B
)
DVDD
CVDD
C
718
M10
VSS
R16
R1
DVDD 0.
1u
K12
DVDD
DVDD
VSS
TMS320D810K003BZKBT
IC701
DVDD
DVDD
C825
USB0_VDDA18
T16
VSS
CVDD
CVDD
2200p
C741
RSV1(OPEN)
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
VDDARNWA
J12
10u
R7J0
R7J1
0
L7A2
L7A1
R7
J6
AFSX1/
AHCLKX1/
ACLKX1/
BOOT[0]/
BOOT[1]/
BOOT[2]/
BOOT[3]/
UART2_TXD/
UART2_RXD/
1SS355
FIN1
D1
2200p
DS
P
_NO
R_
A
D
1L
INE
(1
2..0
)
UHPI_HRDY*/
UHPI_HRW*/
48
2
4
3
27p
4
2
1
3
27p C
734
27p C
730
27p C
742
27p C
710
27p C711
27p C
723
27p
C781
open
27p C
774
27p 27p C771 27p
C
782
open C
775
CPUGND
C1
W4
27p
(CH)
C1
W3
open
(1005)
C1
W0
open
C1W
1
open
R7
G
0
open
R7G
1
open
0.
1u
C
702
C
706
0.
1u
NJM2846DL3-33
0.
1u
C701
R7ND9
D3.3V
open C777
VCC
GND
IC7J4
B
Y
A
EMB_WE_DQM[0]*/
EMB_WE_DQM[1]*/
EMB_WE_DQM[2]*
GPIO1[6]/
GPIO1[10]/
DSP_RESET
R7A9
R7B1
56
R7C2
R7C4
R709
5
13
33
45
open C
778
6.
3V
(B
)
BK1608TS601-T
open
0.1u
10V
USB0_VDDA12USB0_VSSA33
AXR1[0]/
AXR1[1]/
UHPI_HD[10]/
UHPI_HD[11]/
2
(B
)
16V
M
X
29LV
160DB
T
I-70G
IC702
10
C9
D3
3
C1W
7
open
C7
G
3
2200p
1/
16
1/
16
XT
AL
(1005)
100
0
R7J2
100
0.
1u
DSP_RST_OUT
5
5
5
4
DS
P
_DA
RA
M_
DA
TA
LI
NE
(1
5..0
)
(1608)
0.
1u
C
729
2200p
C
739
DVDD
DVDD
9
open
C
780
IC732
6
(1/8W)
PLL0_VSSA
USB0_VDDA33
USB1_VDDA33
VSS
VSS
VSS
VSS
F8
0.
1u
4
C
724
C
720
C
770
RB521G-30
4
DSP_GND2
open C
776
C
772
B2
VSS
VSS
R746
R745
22
R728
82
R729
IO3
IO4
IO6
VDDQ
VDDQ
IO14
A10/AP
CS*
A1
A0
BA1
BA0
RAS*
CAS*
LDQM
VDD
IO7
VSSQ
VSSQ
IO2
A4
VSS
VDD
A2
A8
A3
IO15
VDD
IO0
IO12
A9
IO10
IO9
VSS
N.C
UDQM
CLK
CKE
N.C
A11
A5
A6
A7
VSS
IO13
VDDQ
IO8
WE*
IC703
IS45S16400F-7TLA1
R726
C7307
12
13
10
open
*
(1608)
R714
C
763
0.
1u
C737
C
732
VDDARNWA1
D1.2V
S-1172B12-E6T1G
+2V
GND3
0
*
R7
G
9
E3
USB1_VDDA18
PLL0_VDDA
C
752
(CH) 50V
C755
1u
6.3V
EMB_D[10]/
EMB_D[9]/
EMB_D[8]/
EMB_D[7]/
EMB_D[6]/
GPIO1[4]/
GPIO1[3]/
T12
EMB_D[1]/
L7A0
180 DA_DATA_0
DA_DATA0
UHPI_HD[2]/
UHPI_HD[0]/
UHPI_HAS*/
IC701 TRST*
EMA_CAS*/
EMA_RAS*/
GPIO1[0]/
EMA_SDCKE/
AMUTE0/
N3
DA_DATA_4 180 R7A4
R7A3
R7A2
AUDIO_MUTE_1
AD_LRCK_OUT
+4V
R9
D3
3
L664
6.3V
2
(1/
8W)
R7
G
8
C712 C773 27p
0.
1u
M9
C
735
R798
*
0
6.
3V
C747
L10 G9
VSS
VSS
R727
IO5
FBMH3216HM501NT
(B
)
L7111
DSP_RESETOUT
5357_DATA
DCDC_SHD ADC_GND DAC_GND
DSP_CHECK
DSP_ENA
ADC_GND
D
SP_D
AR
AM
_AD
R
ESSLI
N
E(13.
.0)
DS
P
_DA
RA
M_
CO
NTL
INE
(7
..0
)
R7C7
56
B6
ACLKR0/
AHCLKR0/
AXR0[7]/
AXR0[8]/
EMB_SDCKE
EMB_WE*
AHCLKX0/
ACLKX0/
L7D0
DS
P
_NO
R_
A
D
2L
INE
(5
..0
)
DS
P
_NO
R_
CO
NTL
INE
(3
..0
)
R70G3
R7ND4
R7ND0
VSS
C725
C
722
0.
1u
0.
1u
0.
1u
RSV2(CVDD)
C727
L7D1
L7D2
10k
R72B
IO1
VSSQ
IO11
VSSQ VDDQ
6.
3V
(B
)
C
7202
R710
R764
open
R7R4
R711
C7201
R712
10
R708
R706
R707
R713
DSP3V_DETECT
2
6.3V
82
82
1000p
0.1u
C779
C7313
(CH)
R720
(CH)
L7510
C
7110
22u (B
)
6.
3V
C7314
(B)
C7312
82
0
IC707
L7110
1000p
(B)
FBMH3216HM501NT
C7111 22u
IC-PST8229UR
FBMH3216HM501NT
C7311
0.1u
R721
R722
82
R723 82
R724
C7310 1000p (CH)
C7309 0.1u
(B)
82
0.1u
C7301
0.1u
(B) C7302
1000p
R731
82
(CH)
A
A
A
A
A
A
A
A
A
A
A
A
(1/2)
A
(2/2)
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A A
Copyright (C) Mitsubishi Electric Corporation. Your company internal use only.
SCHEMATIC DIAGRAM MAIN DSP / SDRAM / FLASH MODEL : CV-0MW3R45,-2
23