128
8175 N/B MAINTENANCE
8175 N/B MAINTENANCE
5.3 Intel 82801BA(I/O Controller HUB )
Processor Interface Signals
Name Type
Description
A20M#
O
Mask A20:
A20M# goes active based on setting the appropriate bit in
the Port 92h register, or based on the A20GATE signal.
Speed Strap:
During the reset sequence, ICH2 drives A20M# high if
the corresponding bit is set in the FREQ_STRP register.
CPUSLP#
O
Processor Sleep:
This signal puts the processor into a state that saves
substantial power compared to Stop-Grant state. However, during that
time, no snoops occur. The ICH2 can optionally assert the CPUSLP#
signal when going to the S1 state.
FERR#
I
Numeric Coprocessor Error:
This signal is tied to the coprocessor
error signal on the processor. FERR# is only used if the ICH2
coprocessor error reporting function is enabled in the General Control
Register (Device 31:Function 0, Offset D0, bit 13). If FERR# is
asserted, the ICH2 generates an internal IRQ13 to its interrupt
controller unit. It is also used to gate the IGNNE# signal to ensure
that IGNNE# is not asserted to the processor unless FERR# is active.
FERR# requires an external weak pull-up to ensure a high level when
the coprocessor error function is disabled.
IGNNE#
O
Ignore Numeric Error:
This signal is connected to the ignore error
pin on the processor. IGNNE# is only used if the ICH2 coprocessor
error reporting function is enabled in the General Control Register
(Device 31:Function 0, Offset D0, bit 13). If FERR# is active,
indicating a coprocessor error, a write to the Coprocessor Error
Register (F0h) causes the IGNNE# to be asserted. IGNNE# remains
asserted until FERR# is negated. If FERR# is not asserted when the
Coprocessor Error Register is written, the IGNNE# signal is not
asserted.
Speed Strap:
During the reset sequence, ICH2 drives IGNNE# high
if the corresponding bit is set in the FREQ_STRP register.
INIT#
O
Initialization:
INIT# is asserted by the ICH2 for 16 PCI clocks to
reset the processor. ICH2 can be configured to support processor
BIST. In that case, INIT# will be active when PCIRST# is active.
INTR
O
Processor Interrupt:
INTR is asserted by the ICH2 to signal the
processor that an interrupt request is pending and needs to be
serviced. It is an asynchronous output and normally driven low.
Speed Strap:
During the reset sequence, ICH2 drives INTR high if
the corresponding bit is set in the FREQ_STRP register.
NMI
O
Non-Maskable Interrupt:
NMI is used to force a non-maskable
interrupt to the processor. The ICH2 can generate an NMI when
either SERR# or IOCHK# is asserted. The processor detects an NMI
when it detects a rising edge on NMI. NMI is reset by setting the
corresponding NMI source enable/disable bit in the NMI Status and
Control Register.
Speed Strap:
During the reset sequence, ICH2 drives NMI high if the
corresponding bit is set in the FREQ_STRP register.
Name Type
Description
SMI#
O
System Management Interrupt:
SMI# is an active low output
synchronous to PCICLK. It is asserted by the ICH2 in response to one
of many enabled hardware or software events.
STPCLK#
O
Stop Clock Request:
STPCLK# is an active low output synchronous
to PCICLK. It is asserted by the ICH2 in response to one of many
hardware or software events. When the processor samples STPCLK#
asserted, it responds by stopping its internal clock.
RCIN#
I
Keyboard Controller Reset Processor:
The keyboard controller can
generate INIT# to the processor. This saves the external OR gate with
the ICH2’s other sources of INIT#. When the ICH2 detects the
assertion of this signal, INIT# isgenerated for 16 PCI clocks..
Note:
82801BA ICH2: The 82801BA ignores RCIN# assertion during
transitions to the S3, S4 and S5 states. 82801BAM ICH2-M: The
82801BAM ignores RCIN# assertion during transitions
to the S1, S3, S4 and S5 states.
A20GATE
I
A20 Gate:
This signal is from the keyboard controller. It acts as an
alternative method to force the A20M# signal active. A20GATE
saves the external OR gate needed with various other PCIsets.
CPUPWRGD
OD
CPU Power Good (82801BAM ICH2-M):
This signal should be
connected to the processor’s PWRGOOD input. For Intel®
SpeedStep™ technology support, this signal is kept high during a
Intel® SpeedStep™ technology state transition to prevent loss of
processor context. This is an open-drain output signal (external
pull-up resistor required) that represents a logical AND of the
ICH2-M’s PWROK and VGATE / VRMPWRGD signals.
SM Bus Interface Signals
Name Type
Description
SMBDATA
I/OD
SMBus Data:
External pull-up is required.
SMBCLK
I/OD
SMBus Clock:
External pull-up is required.
SMBALERT#
/
GPIO[11]
I
SMBus Alert:
This signal is used to wake the system or generate an
SMI#. If not used for SMBALERT#, it can be used as a GPI.
