Midas RTE-V831-PC, Руководство пользователя

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RTE-V831-PC USER’S MANUAL (Rev. 2.00)
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10. EXT BUS SPECIFICATIONS
The EXT bus, provided with JEXT connectors, is used to expand the memory and I/O units. The local bus
of this board is connected to the JEXT connector.
10.1. PIN ARRANGEMENT AND SIGNALS
The following table shows the pin arrangement of the JEXT connector. The signals on these pins are
also explained below.
Number Signal name Number Signal name Number Signal name Number Signal name
1 +5V 2 +5V 31 GND 32 GND
3 D0 4 D1 33 A8 34 A9
5 D2 6 D3 35 A10 36 A11
7 D4 8 D5 37 A12 38 A13
9 D6 10 D7 39 A14 40 A15
11 GND 12 GND 41 +5V 42 +5V
13 D8 14 D9 43 A16 44 A17
15 D10 16 D11 45 A18 46 A19
17 D12 18 D13 47 BHE- 48 GND
19 D14 20 D15 49 GND 50 RD-
21 +5V 22 +5V 51 WR- 52 RESET-
23 A0 24 A1 53 GND 54 GND
25 A2 26 A3 55 READY 56 INT-
27 A4 28 A5 57 GND 58 GND
29 A6 30 A7 59 CPUCLK 60 GND
JEXT Connector Pin Arrangement
Signal name Input/output Function
A[1..19] Output Address bus signal, connected to the CPU address signal via a buffer
A0, BHE- Output Byte low/high enable signal
D[0..15] Input/output Data bus signal, connected to the CPU data bus signal via a buffer
It is pulled up with a 10-k
Ω
resistor on the board.
RD- Output Read cycle timing signal, which becomes active only when the JEXT space is
accessed.
WR- Output Write cycle timing signal, which becomes active only when the JEXT space is
accessed.
READY Input Signal for notifying the V831 of the end of a cycle. It is valid for the JEXT
space. To have the V831 reliably recognize READY, it is necessary to keep
READY active until RD- or WR- becomes inactive. It is pulled up with a 10-k
Ω
resistor on the board.
INT- Input Active-low interrupt request signal. It is logically inverted and connected to the
INTP01 pin of the V831 via a buffer.
RESET- Output Active-low system reset signal
CLK Output Clock signal, connected to the CLKOUT pin of the V831 via a buffer.
JEXT Connector Signals