RTE-V831-PC
USER’S MANUAL (Rev. 2.00)
13
7.2.
DETAILS OF MAPPING
Detailed information on mapping is provided below.
CS0 space (x000-000 to x0FF-FFFF, x800-000 to x8FF-FFFF)
CS0 is the space for EDO-DRAM mounted in the SIMM#1 and SIMM#2 sockets. The size of the CS0
space is 16M bytes while it has a data bus width of 32 bits. The lower 8M bytes are mapped onto
SIMM#1, while the higher 8M bytes are mapped onto SIMM#2. In the other space, an image appears at
intervals of 16M bytes.
For interfacing with DRAM, the DRAM controller built into the V831 is used.
CS1 space (x100-000 to x1FF-FFFF, x900-000 to x9FF-FFFF)
CS1 is not used.
CS2 space (x200-000 to x27F-FFFF, xA00-000 to xA7F-FFFF)
CS2 is the space for flash ROM (MBM29F016PFTN-120 manufactured by Fujitsu: 2M
×
8 bits, 120 ns).
The size of the CS2 space is 8M bytes while it has a data bus width of 32 bits. A flash ROM image
appears at intervals of 8M bytes.
Wait control is exercised by external hardware. Four wait clock cycles are always inserted.
CS3 space (x300-000 to x3FF-FFFF, xB00-000 to xBFF-FFFF)
CS3 is not used.
CS4 space (x400-000 to x40F-FFFF, xC00-000 to xC0F-FFFF)
CS4 is the 1M-byte extension bus space. This space is assigned as memory or I/O space by the V831's
internal bus controller. An extension bus space image appears at 1M-byte intervals.
Wait control is exercised by external hardware. After two wait clock cycles have been inserted, wait
control (ready) is exercised from the extension bus.
Before attempting to use this space, see Section 10.3.
CS5 space (x500-000 to x5FF-FFFF, xD00-000 to xDFF-FFFF)
CS5 is the space for I/O devices including the timer, audio channels, and serial and parallel channels
mounted on the board. The bus controller must be set to enable the assigning of this space as a 16-bit
I/O space. Because full decoding is not performed, image spaces appear at various locations. So,
never attempt to access other than the specified I/O addresses.
Wait control is exercised by external hardware. One wait clock cycle is always inserted for high-speed
I/O, while seven wait clock cycles are always inserted for low-speed I/O.
For details of each I/O device, see Chapter 8.
CS6 space (x600-000 to x6FF-FFFF, xE00-000 to xEFF-FFFF)
CS6 is the space for high-speed SRAM (
m
PD431008LE-15 manufactured by NEC: 128K
×
8 bits, 15 ns).
The size of the CS6 space is 512K bytes while its data bus width is 32 bits. An SRAM image appears at
512K-byte intervals.
Wait control is exercised by the bus controller built into the CPU. Access is possible with no wait clock
cycles when a 33-MHz external clock is used.
CS7 space (x700-000 to x7FF-FFFF, xF00-000 to xFFF-FFFF)
CS7 is the space for boot ROM. When the 16-bit bus (BT16B = 1) is selected, the EPROM is selected
as boot ROM. When the 32-bit bus is selected, the flash ROM is selected as the boot ROM. (The
setting of pin BT16B can be switched using SW1-8.)
As an EPROM, a 27C1024, or 27C2048 (150 ns or less) (40-pin DIP type) can be used. The evaluation
board is factory-fitted with a 27C1024 incorporating the monitor.
Wait control is exercised by external hardware. Five wait clock cycles are always inserted for the
EPROM, while four wait clock cycles are always inserted for the flash ROM.
