Midas RTE-V821-PC, Руководство пользователя

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RTE-V821-PC USER’ S MANUAL
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EXT-BUS (8010-0000H to 801F-FFFFH)
This space is used for a hardware expansion board connected to the JEXT connector on the
RTE-V821-PC. See Chapter 7 for details of the EXT-BUS.
SRAM space (FF00-0000H to FF01-FFFFH)
This space is provided in SRAM on the board. Its capacity is 256 Kbytes. SRAM can be
accessed with no wait state.
SYSTEM-I/O (FFB0-0000H to FFB0-0FFFH)
This space is assigned to I/O devices for controlling each function on the board. It acts as
memory-mapped I/O units. See Chapter 6 for details.
ROM (FFFE-0000H to FFFF-FFFFH)
This space is provided in ROM on the board. Its storage capacity is 256 Kbytes. Three wait
states are inserted in a ROM access cycle during ready signal control. If the CPU clock
frequency is 25 MHz, the access time of the ROM must be 150 ns or less.
The standard ROM chip that is factory-set contains the Multi monitor.
5.2. I/O MAP
The I/O space in the V821-CPU is not used in the RTE-V821-PC. The I/O registers used for
control purposes are allocated in the memory-mapped SYSTEM-I/O space. This section
explains how to set the internal I/O registers.
Some part of the CPU internal I/O registers is used for controlling the hardware of the RTE-
V821-PC. When a user program specifies an I/O register in the CPU, it is necessary to pay
attention to the state of the internal I/O registers used in the system.
5.2.1. Port Unit (PORT)
Of P00 to P09, P08 should be fixed at UBE-. The related internal I/O ports are listed below.
Register I/O address Setting
PMC0 C000-0010H 0000-00x1-xxxx-xxxxB
PM0 C000-0012H 0000-00x0-xxxx-xxxxB
P0 C000-0014H 0000-00xx-xxxx-xxxxB
Port Unit Setting
5.2.2. Wait Control Unit (WCU)
The following table lists the way the CS0- to CS3- signals output from the CPU are used.
Area Type WCU-WAIT External wait
CS0- Memory DRAM(REFRQ-) --- (by DRAMC) (See Section 5.2.3.)
CS1- Memory SRAM 0 Used
CS2- Memory SRAM 0 Used
CS3- Memory SRAM 0 Used
Use of WCU