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System Core, Boot Configuration and On-Board Memory 5
miriac SBC-LS1046A-TSN_User Manual
V 2.0
25/68
© MicroSys Electronics GmbH 20178
5.4
Clock Distribution
The following diagram shows the clock distribution of the SBC-LS1046A-TSN
system
LS1046A
ST4
ST1
Pin
Name
Signal
Pin
Signal
Pin
P3
SDHC_CL
K
→
10R
→
LVL
SHIFT
→
SDC-
CLK
B100
→ →
→
SDC-
CLK-
EMI
5
N1
IIC1_SCL
→
→
→
→
→
I2C1-
SCL
B78
→
→
→
See chapter
5.8.1
K3
IIC2_SCL
→
→
→
→
→
I2C2-
SCL
B75
→
→
→
See chapter
5.8.2
JTG1
E18
TCK
→
→
→ →
→
JTCK
B105
→
10R
→
JTCK
6
J14
W4
EC1_TX_
CLK
→
10R
→ →
→
MII1-
TXCK
T94
→ →
→
TX_CLK
53
W1
EC1_RX_
CLK
←
10R
← ←
←
MII1-
RXCK
T86
←
10R
←
RX_CLK
46
AC3
EC1_GTX
_CLK125
←
10R
← ←
←
MII1-
CRS
T83
← ←
←
CLK125
9
JP1
U2
SPI_CLK
→
10R
→
LVL
SHIFT
→
SPI-
CLK
B69
→ →
→
SPI-CLK
1