System Core, Boot Configuration and On-Board Memory 5
miriac SBC-LS1046A-TSN_User Manual
V 2.0
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© MicroSys Electronics GmbH 20178
5
System Core, Boot Configuration
and On-Board Memory
5.1
Processor NXP LS1046A
The LS1046A Processor by NXP is a QorIQ Layerscape CPU with four CPU cores.
It exposes a wide variety of external interfaces, which are explained in detail in the
following chapters. The cores have an unified L2 Cache.
The four CPU cores run at a maximum clock speed of 1800 MHz, 1600 MHz, 1400
MHz or 1200 MHz respectively, depending on the ordered type. The CPU
frequency can be clocked down if necessary.
5.2
JTAG Chain
The JTAG chain of the SBC-LS1046A-TSN includes the LS1046A processor only.
The JTAG port is directly connected to the connector
“JTG1”.
The JTAG connector footprint provides JTAG signals. For interfacing standard de-
bugger pinouts an additional intermediate adapter is necessary.
Please see chapter 0 for a description of the JTAG connector.
5.3
Reset Structure
Figure 5-1 Reset Structure (carrier CRX06 Revision 2)
