Board Components and Operations
UG0747 User Guide Revision 1.0
20
The following figure shows the FTDI interface of the PolarFire Evaluation Board.
Figure 13 •
FTDI Interface
4.7
System Reset
DEVRST_N is an input-only reset pad that allows assertion of a full reset of the chip at any time. The
DEVRST_N signal (active-low) is asserted in the following cases:
Information to be added.
4.8
50 MHz Oscillator
A 50 MHz clock oscillator with an accuracy of +/-50 ppm is available on the board. This clock oscillator is
connected to the FPGA fabric to provide a system reference clock.
An on-chip PolarFire PLL can be configured to generate a wide range of high-precision clock
frequencies.
The following table provides package and pin details of the 50 MHz oscillator.
The following figure shows the 50 MHz clock oscillator interface.
Figure 14 •
50 MHz Clock Oscillator
For more information, see the Board-Level Schematics document (provided separately).
4.9
User Interface
The PolarFire Evaluation Board has user LEDs as well as push-button switches.
Table 7 •
Pin Details of 50 MHz Oscillator
Pin Number Pin Name
E25
HSIO63PB6/CLKIN_S_12/CCC_SE_CLKIN_S_12/CCC_SE_PLL0_OUT0
)7
86%PLQL%
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08;
8
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8
8
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-
-
08;
8
63,
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8
6
6
6
63,
6,*1$/6
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6,*1$/6
8$57
-
8$57
6,*1$/6
6
63,
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9
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