Board Components and Operations
UG0747 User Guide Revision 1.0
16
•
TX pad > via (to bottom layer) > trace > AC coupling > trace > via (to top layer and Inner layer)
> RX pad.
The XCVR2 reference clock is routed from the on-board LVDS MUX chip and the default setting is 122.8
MHz and 125 MHz clock is routed to MUX chip.
The expected Clock Mux outputs are as follows:
•
Voltage level: 3.3 (± 0.3) V
•
Differential LVDS
•
Symmetry: 50% (± 10%)
•
Differential output voltage: 250 mV minimum, 350 mV Typical, 500 mV maximum
The following figure shows the XCVR2 interface of the PolarFire Evaluation Board.
Figure 9 •
XCVR2 Interface
For information about the J46 jumper, see
Table 3, page 8
.
For more information, see the Board-Level Schematics document (provided separately).
4.3.4
XCVR Reference Clocks
The XCVR supports the reference clocks connected as follows:
•
XCVR 1B,1C, and 3C Reference clocks are connected to FMC HPC connector
•
XCVR 2B Reference clock is connected to external SMA connector(J40 and J44)
•
XCVR 2C Reference clock is connected on board 156.25 MHz oscillator
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