Microsemi LX7720, Руководство пользователя

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Control and Acquisition Signals Headers J10 and J20
June 2020 LX7720 Daughter Board rev 2.1 17
© 2020 Microsemi Corporation
4.14 Motor Connections
Standard connections for the 24V, 8 phase, 3 pole BLDC motor used to develop the RTG4
programming are J9 pin 1: yellow (coil A), pin 2: red (coil B), pin 3: black (coil C).
1
2
3
4
J9
OSTOQ047150
MTR_COIL_A
MTR_COIL_B
MTR_COIL_C
MTR_COIL_D
.
.
Figure 21. Motor Winding Connections Schematic
5 Control and Acquisition Signals Headers J10 and J20
J20 is a 2x20 pin 0.1" pitch pin header which provides buffered control signals to an external controller (such as
J10 provides direct connection to the HPC1-FMC (FPGA Mezzanine Card) connectors on the
and
. Table 14 below shows the FPGA pin routing for each LX7720 pin on these kits.
FMC
Pin
LX7720 Signal
Name
LX7720 Signal Type and Function
RTG4 Pin
Number
RTG4 Pin
Name
PolarFire
Pin Number
PolarFire Pin
Name
C11 ADC1_C Buffered ADC2 bit stream output J11 MSIO248NB6 G16 GPIO5NB2
C27 UD_IN_A_C Buffered UD_IN_A FET drive input A8 MSIO261NB6 D6 GPIO13NB2
D27 LD_IN_C_C
Buffered LD_IN_C FET drive input B8 MSIO252NB6 G11 GPIO18NB2
E10 UD_IN_B_C
Buffered UD_IN_B FET drive input F18 MSIO287NB5 T4 GPIO217NB4
F7 UD_IN_C_C Buffered UD_IN_C FET drive input J19 MSIO296PB5 AB9 GPIO183PB4
F8 LD_IN_B_C Buffered LD_IN_B FET drive input H19 MSIO296NB5 AA8 GPIO183NB4
F11 LD_IN_A_C
Buffered LD_IN_A FET drive input F20 MSIO299NB5 AB6 GPIO179NB4
F13 SNS_OUT_A_C
Buffered SNS_OUT_A bit stream output D19 MSIO294PB5 T7 GPIO218PB4
F14 SNS_OUT_B_C Buffered SNS_OUT_B bit stream output C19 MSIO294NB5 U7 GPIO218NB4
F19 BLO4 Bi-Level Detector output 4 C13 MSIO277PB5 AB4 GPIO177PB4
G9 ADC3_C
Buffered ADC3 bit stream output K10 MSIO242PB6 H16 GPIO32PB2
G16 RESET RESET input via J40 link header G15 MSIO269NB6 E12 GPIO23NB2
G18 OTW_FAULT OTW_FAULT output D11 MSIO268PB6 D10 GPIO26PB2
G21 CP_CLK_C
Buffered 150kHz ±50kHz CP_CLK charge
pump clock input
B10 MSIO270PB6 B9 GPIO25PB2
G24 DMOD_IN_P_C Buffered DMOD_IN_P drive input B5 MSIO255PB6 D8 GPIO14PB2
G25 UD_IN_D_C
Buffered UD_IN_D FET drive input B6 MSIO255NB6 C8 GPIO14NB2
G28 BLO6
Bi-Level Detector output 6 C6 MSIO246NB6 H11 GPIO4NB2
G30 BLO5 Bi-Level Detector output 5 C3 MSIO243PB6 B10 GPIO28PB2
G31 BLO3 Bi-Level Detector output 3 B3 MSIO243NB6 A10 GPIO28NB2
H7 CLK_OUT_C
Buffered CLK_OUT Σ-Δ mod clock output H8 MSIO245PB6 L19 GPIO34PB2
H8 MOD_CLK_C
Buffered 24MHz to 32MHz MOD_CLK Σ-Δ
modulator clock input
H9 MSIO245NB6 L18 GPIO34NB2
H10 ADC2_C
Buffered ADC2 bit stream output F9 MSIO258PB6 J18 GPIO33PB2
H13 SNS_OUT_D_C Buffered SNS_OUT_D bit stream output G10 MSIO257PB6 K15 GPIO0PB2
H14 SNS_OUT_C_C Buffered SNS_OUT_C bit stream output G11 MSIO257NB6 J15 GPIO0NB2
H17 SM_EN
SM_EN input via J39 link header D14 MSIO273NB6 K17 GPIO35NB2
H19 OC_FAULT
OC_FAULT output E9 MSIO259PB6 A7 GPIO16PB2
H20 PR_FAULT PR_FAULT output D9 MSIO259NB6 A8 GPIO16NB2
H23 DMOD_IN_N_C Buffered DMOD_IN_N drive input C9 MSIO256NB6 B6 GPIO17NB2
H25 LD_IN_D_C
Buffered LD_IN_D FET drive input A4 MSIO247PB6 H13 GPIO1PB2
H34 BLO2 Bi-Level Detector output 2 F7 MSIO249PB6 G10 GPIO21PB2
H35 BLO1 Bi-Level Detector output 1 F8 MSIO249NB6 F10 GPIO21NB2
K23 SCP
SCP input via J38 link header C16 MSIO282NB5 AB1 GPIO176NB4
Table 14. Mapping of HPC1-FMC pins, LX7720 pins, and RTG4 and PolarFire FPGA pins on the EVBs