ZLR964222L
Line Module User Guide
37
Microsemi Corporation Confidential and Proprietary
7.0 Printed Circuit Board Documentation
7.1 Revision Information
ZLR964222L
Revision A0: Initial Release
ZLR964222L
Revision A1: Soldermask fix.
ZLR964222L Revision B3: Updated BBABS supply, new layout
7.2 Parts Placement Strategy
The
ZLR964222L Line Module
is designed using a two-layer PCB to demonstrate a low cost and compact design.
The design features a
Le9642 miSLIC
TM
Subscriber Line Interface Device
,
Telcordia
-compliant intra-building
protection, and a 2 battery buck-boost ABS swticher. The switcher is optimized for +12 V input. The PCB is
designed with an emphasis on maximum thermal performance for the Microsemi
Le9642
device. This module
measures 3.95" x 2.0" (10 x 5.1 cm). This board is designed to be plugged into the
SM2
expansion receptacle on
the Microsemi
ZTAP (Le71HP0400)
platform.
Good placement and routing are critical for optimal device performance. For best performance, all sense input nets
should be kept as short as possible with their associated components placed close to the
Le9642
device. These
include the following: TDC
1,2
, RDC
1,2
, TAC
1,2
, RAC
1,2
, RSN
1,2
, SWIS
Y,Z
, SWVS
Y,Z
, and SWCMP
Y,Z
. Also, the
VREF net should be routed as directly as possible between the CHL
1
and CHL
2
capacitors, and CREF
1
should be
placed near the VREF pin. Avoid routing the VREF net near any digital signals. It is also recommended that CREF
1
,
CHL
1
and CHL
2
be ceramic capacitors with X5R/X7R dielectric. If a design is expected to operate above 70°C then
X7R capacitors are recommended. Use of Y5V and Z5U type capacitors is not recommended. There are no Y5V or
Z5U type capacitors used in this design.
The switching power supply tends to be the most common place for design and layout mistakes. Switcher
compensation components RCMP
1
and CCMP
1
should be placed as close to pins SWCMPx and SWVSx as
possible. The SWVSx node is a summing node for the error amplifier and should be treated as such. Avoid routing
any digital signals or other sources of noise near this node. Noise on SWCMPx can upset the operation and
efficiency of the switching power supply. CCMP
1,2
should be high quality capacitors with stable characteristics.
NP0/C0G dielectric is preferable especially if the design will experience wide temperature extremes. X7R types are
acceptable for most applications. The SWISx (SWISY, SWISZ) current sense nodes are also very sensitive to
noise. Avoid routing SWISx near the SWOUTY/SWOUTZ signals, the base node, or collector node of the PNP
power transistor (Q1). SWIS should tap right off of the current sense resistors, RLIM
1-4
, and route directly to the
current sense filter components CCS
1
, RCS
1
, and RTH
1
which should be placed near the SWISY pin. CCS
2
should
be placed near the SWISZ pin. Note that for this design, SWIS routes to both SWISY and SWISZ pins. It is
recommended to shield SWIS with ground. The threshold for the SWISY and SWISZ pins is only 100 mV which
makes them very sensitive to noise. Poor routing of SWIS is one of the most common mistakes. A noisy SWIS
signal WILL cause the supply to run poorly. The current limit sense resistors, RLIM
1-4
, should terminate to ground
with multiple vias and minimal trace length from the resistor to ground.
High current nets should be kept short and routed with 25 mil nets minimum. The 12 V net should also be routed
with heavy copper to minimize losses. When the PNP power transistor switches on, the current is sourced primarily
from CSW
1
. The loop from CSW
1
through the transistor Q
1
, inductor L
1
, and RLIM
1
to ground should be as tight as
possible. The ground return from RLIM
1-4
to CSW
1
should be as short as possible. The same is true for the loop to
the output from the inductor to DSW
1
and to the output capacitors CFL
1
/CFL
2
and back to ground.
Following the recommendations above will help achieve best performance and also best EMI/EMC performance.
Additional recommendations for EMI/EMC performance are proper supply decoupling/filtering and good digital
design techniques. DVDD pins should have 0.01 uF decoupling caps and AVDD pins should have 0.1 µF
decoupling caps for each supply pin of the device. An additional bulk decoupling cap such as a 4.7 µF ceramic or
tantalum near the device is also recommended. There is also a filter between DVDD and AVDD that is required. A
