EVB-SEC1110/EVB-SEC1210/EVB-SEC1212-DEV
Evaluation Board User’s Guide
DS00001574A-page 12
2013 Microchip Technology Inc.
• Supports Suspend, Resume, and Remote Wakeup per the USB specification
requirements
• Endpoint buffer may be located anywhere in the 1.5K SRAM, as per the alignment
requirements based on the max packet size
1.2
SEC1210 FEATURES
Along with the features mentioned in Section 1.1, the SEC1210 includes two Smartcard
slots and the following additional features:
1.2.1
SPI1
• Supports full-duplex mode
• Supports master or slave mode
• Supports seven SPI1 Master baud rates
• Slave Clock rate up to spi1_clk/8
• Serial clock with programmable polarity and phase
• Master Mode fault error flag with MCU interrupt capability
• Write collision flag protection
• Byte Transfer/Receive APIs
• Bulk Transfer/ Receive APIs
• Simultaneous Transfer/ Receive APIs
1.2.2
UART
• Software compatible with Standard 16C450 and 16C550A
• Separate 16 byte FIFO for transmission and reception
- Prevents buffer overrun
- Helps software to be less time critical in handling transmission / reception
• Programmable baud rate generator - Up to 3 Mbps baud rate can be achieved
• Supports flow control using RTS / CTS signals
• Pin Polarity control
• Programmable communication parameters:
- Word length - 5, 6, 7, 8 bits
- Stop bits - 1, 1.5, 2 bits
- Parity - None, Odd, Even, Mark, Space
• Low power sleep mode available
1.3
SEC1212-DEV FEATURES
Along with the features mentioned in section 1.1 and1.2 the following modules are also
available in the SEC1212-DEV:
• Boot from SPI2 Interface
• The SVB is equipped with a 1Kbyte Atmel SPI flash (AT26DF081A-SSU). SPI
flash from Atmel and Windbond are supported.
• On-board RS232 Transceiver for debugging as well as RS232 host interface
• On-board Reset button
• On-board EDP header for f/w debugging.
• On-board JTAG header for entering ASIC test mode and debugging
Note:
A voltage level shifter board / cable is required to connect the UART port to
the PC. An FTDI cable is used for this.
