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Important:
Compared to SAMA5D2 Series devices, some PIO features are not listed. These features are
used internally on the SAMA5D27-WLSOM1 and cannot be shared with other PIOs for use with features or
for signal integrity.
3.2.1
PIOA Pin Description
Table 3-1. PIOA Pin Description
Pad No. Power Rail
I/O Type
Primary
Alternate
PIO Peripheral
Reset State (Signal, Dir, PU, PD, HiZ, ST)
Note
Signal Dir Signal Dir Func
Signal
Dir IO Set
W11
VDDSDHC GPIO_EMMC
PA0
I/O
–
–
A
SDMMC0_CK
I/O
1
PIO, I, PU, ST
B
QSPI0_SCK
O
1
F
D0
I/O
2
R9
VDDSDHC GPIO_EMMC
PA1
I/O
–
–
A
SDMMC0_CMD
I/O
1
PIO, I, PU, ST
B
QSPI0_CS
O
1
F
D1
I/O
2
W12
VDDSDHC GPIO_EMMC
PA2
I/O
–
–
A
SDMMC0_DAT0
I/O
1
PIO, I, PU, ST
B
QSPI0_IO0
I/O
1
F
D2
I/O
2
V11
VDDSDHC GPIO_EMMC
PA3
I/O
–
–
A
SDMMC0_DAT1
I/O
1
PIO, I, PU, ST
B
QSPI0_IO1
I/O
1
F
D3
I/O
2
W14
VDDSDHC GPIO_EMMC
PA4
I/O
–
–
A
SDMMC0_DAT2
I/O
1
PIO, I, PU, ST
B
QSPI0_IO2
I/O
1
F
D4
I/O
2
V10
VDDSDHC GPIO_EMMC
PA5
I/O
–
–
A
SDMMC0_DAT3
I/O
1
PIO, I, PU, ST
B
QSPI0_IO3
I/O
1
F
D5
I/O
2
W15
VDDSDHC GPIO_EMMC
PA6
I/O
–
–
A
SDMMC0_DAT4
I/O
1
PIO, I, PU, ST
Note (2)
B
QSPI1_SCK
O
1
D
TIOA5
I/O
1
E
FLEXCOM2_IO0
I/O
1
F
D6
I/O
2
W16
VDDSDHC GPIO_EMMC
PA7
I/O
–
–
A
SDMMC0_DAT5
I/O
1
PIO, I, PU, ST
Note (2)
B
QSPI1_IO0
I/O
1
D
TIOB5
I/O
1
E
FLEXCOM2_IO1
I/O
1
F
D7
I/O
2
SAMA5D27 Wireless SOM1
Pinout
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2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS60001590D-page 8