...........continued
Pad No. Power Rail
I/O Type
Primary
Alternate
PIO Peripheral
Reset State (Signal, Dir, PU, PD, HiZ,
ST)
Note
Signal Dir Signal Dir Func
Signal
Dir IO Set
A2
VDD_3V3
GPIO
PB30
I/O
–
–
C
FLEXCOM0_IO2 I/O
1
PIO, I, PU, ST
Note (3)
D
TCLK5
I
2
F
ISI_D4
I
3
J4
VDD_3V3
GPIO
PB31
I/O
–
–
C
FLEXCOM0_IO3
O
1
PIO, I, PU, ST
Note (3)
F
ISI_D5
I
3
Notes:
1.
Fixed feature due to the WLSOM1 internal connection.
2.
Limited feature compared to SAMA5D2 due to the WLSOM1 internal use of specific functionality, for example,
QSPI, GMAC.
3.
Limited feature compared to SAMA5D2 due to the use of a part of the functionality for other features in the
WLSOM1, for example, GMAC, ISC, FLEXCOM, etc.
3.2.3
PIOC Pin Description
Table 3-3. PIOC Pin Description
Pad No.
Power Rail
I/O Type
Primary
Alternate
PIO Peripheral
Reset State (Signal, Dir, PU, PD, HiZ, ST)
Note
Signal Dir Signal Dir Func
Signal
Dir IO Set
T14
VDD_3V3
GPIO
PC0
I/O
–
–
C
FLEXCOM0_IO4
O
1
PIO, I, PU, ST
Note (3)
F
ISI_D6
I
3
R16
VDD_3V3
GPIO
PC1
I/O
–
–
C
CANTX0
O
1
PIO, I, PU, ST
Note (3)
D
SPI1_SPCK
I/O
1
E
I2SCK0
I/O
1
F
ISI_D7
I
3
T15
VDD_3V3
GPIO
PC2
I/O
–
–
C
CANRX0
I/O
1
PIO, I, PU, ST
Note (3)
D
SPI1_MOSI
I/O
1
E
I2SMCK0
O
1
F
ISI_D8
I
3
T13
VDD_3V3
GPIO
PC3
I/O
–
–
C
TIOA1
I/O
1
PIO, I, PU, ST
Note (3)
D
SPI1_MISO
I/O
1
E
I2SWS0
I/O
1
F
ISI_D9
I
3
P16
VDD_3V3
GPIO
PC4
I/O
–
–
C
TIOB1
I/O
1
PIO, I, PU, ST
Note (3)
D
SPI1_NPCS0
I/O
1
E
I2SDI0
I
1
F
ISI_PCK
I
3
SAMA5D27 Wireless SOM1
Pinout
©
2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS60001590D-page 12