Figure 5-4. ATSAMA5D27-WLSOM1-EK1 Schematic: Page 4
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4 of 6
SAMA5D27-WLSOM1 Evaluation Kit
10/10/2019 3:37:58 PM
03 - User interface.SchDoc
Project Title
Sch #:
Date:
File:
Revision:
Sheet
Designed with
Drawn By:
DD
Sheet Title
User interface
Engineer:
RC
03-10984
1
Size
A3
SAMA5D27-WLSOM1-EK1
PartNumber:
Variant Name
Standard
Altium.com
1
4
2
3
TACT SPST
SW1
WKUP
1
4
2
3
TACT SPST
SW2
1
4
2
3
TACT SPST
SW3
nSTART_SOM
USER_BUTTON_PB02
GND
G
R
EE
N
BL
U
E
2
1
R
ED
4
3
RED, GREEN, BLUE
LD1
LED_RGB_CLV1A
VDD_3V3
GND
i
SDMMC
Matched Net Lengths [Tolerance = 0.25mm]
68k
0402
5%
R81
4.7uF
10V
0402
C5
1
4
2
3
TACT SPST
SW4
100R
0402
5%
R70
100R
0402
5%
R71
100R
0402
5%
R72
100R
0402
5%
R73
10k
0402
R74
NRST
3
1
2
BSS138
Q1
GND
100R
0402
5%
R62
3
1
2
BSS138
Q2
GND
100R
0402
5%
R63
3
1
2
BSS138
Q3
GND
100R
0402
5%
R64
2.2k
0402
5%
R65
2.2k
0402
5%
R66
1k
0402
5%
R68
RED_LED_PA06
GREEN_LED_PA07
BLUE_LED_PA08
470R
0402
5%
R67
EARTH_ETH
GND_ETH
VDD_3V3
EARTH_ETH
EARTH_ETH
ETH_TX_P
ETH_TX_N
ETH_RX_P
ETH_RX_N
i
ETHERNET
ETH_LED0
OE
1
A
2
Y
4
GND
3
VCC
5
NL17SZ125-D
U2
JP2
1
2
J8
10k
0402
1%
R77
VDD_3V3
0.1uF
10V
0402
C3
10k
0402
R82
DNP
QSPI_CS_PB6
NCS_QSPI
DAT3
1
CMD
2
VSS1
3
VDD
4
CLK
5
VSS2
6
DAT0
7
DAT1
8
DAT2
9
CD
10
WP
11
SHIELD
12
SD
J9
GND
VDD_3V3
10k
0402
1%
R84
10k
0402
1%
R83
10k
0402
1%
R76
68k
0402
5%
R80
68k
0402
5%
R79
68k
0402
5%
R78
VDDSDHC
SD/MMC INTERFACE
Disable Boot QSPI Memory
GND
GND_ETH
0R
0402
R69
0.1uF
10V
0402
C2
0.1uF
10V
0402
C1
SDMMC0_WP_PA12
SDMMC0_DAT2_PA04
SDMMC0_CMD_PA01
SDMMC0_DAT3_PA05
SDMMC0_CLK_PA00
SDMMC0_DAT0_PA02
SDMMC0_DAT1_PA03
SDMMC0_CD_PA13
100k
0402
R156
VDDBU
VDDBU
Jumper on = Disable
10000pF
50V
0402
C23
22R
0402 1%
R75
22R
0402 1%
R94
22R
0402 1%
R96
22R
0402 1%
R157
22R
0402 1%
R158
22R
0402 1%
R159
0.1uF
10V
0402
C4
120R
BLM18PG121SN1D
FB5
DIFF100
DIFF100
DIFF100
DIFF100
10k
0402
1%
R95
10k
0402
1%
R166
GND
GND
TD+
TD-
RD-
RD+
TCT
RCT
1nF
75R
75R
75R
75R
TX+
TX-
RX+
RX-
Green
Yellow
1
2
3
4
5
6
7
8
Right
Lift
3
1
2
5
6
4
10
9
8
SH
D
11
12
JD2-0010NL
J6
CON RJ-45 JD2-0010NL
100
Ω
±5
Ω
differential trace impedance
Routing top or bottom
50
Ω
± 10% single-ended trace impedance
A
TSAMA5D27-WLSOM1-EK1
Appendix: Schematics and Layouts
©
2019 Microchip T
echnology Inc.
User Guide
DS50002931A-page
50