Table 3-10. JTAG Connector Pin Assignment
Pin No
Function
PIO
Signal
1
3.3V Supply Voltage
–
VDD_3V3
2
3.3V Supply Voltage
–
VDD_3V3
3
Not used
–
NC
4
GROUND
–
GND
5
JTAG data input into target processor
PD28
JTAG TDI
6
GROUND
–
GND
7
JTAG mode set input into target processor
PD30
JTAG TMS
8
GROUND
–
GND
9
JTAG clock signal into target processor
PD27
JTAG TCK
10
GROUND
–
GND
11
Not used
–
NC
12
GROUND
–
GND
13
JTAG data output from target processor
PD29
JTAG TDO
14
GROUND
–
GND
15
Active-low reset signal. Target processor reset signal.
NRST
NRST
16
GROUND
–
GND
17
Not used
–
NC
18
GROUND
–
GND
19
Not used
–
NC
20
GROUND
–
GND
3.6.2
Debug UART
The ATSAMA5D27-WLSOM1-EK1 board has a dedicated serial port for debugging, which is accessible through the
6-pin male header J26. Various interfaces can be used as a USB/Serial DBGU port bridge, such as FTDI TTL-232R
USB to TTL serial cable or basic breakout board for the RS232/USB converter.
ATSAMA5D27-WLSOM1-EK1
Baseboard Components
©
2019 Microchip Technology Inc.
User Guide
DS50002931A-page 30