Memotech Limited MTX 500, Руководство по обслуживанию

Страница: 18 / 78

14
Pin Description
B/A.
Channel A Or B Select (input, High selects channel
B). This input defines which channel is accessed
during a data transfer between the CPU and the Z-
80 DART.
C/D.
Control Or Data Select (input, High selects
Control). This input specifies the type of
information (control or data) transferred on the
data bus between the CPU and the Z-SO DART.
CE.
Chip Enable(input, active Low). A Low at this
input enables the Z-80 DART to accept command or
data input from the CPU during a write cycle, or
to transmit data to the CPU during a read cycle.
CLK.
System Clock (input). The Z-80 DART uses the
standard Z-80 single-phase system clock to
synchronize internal signals.
CTSA, CTSB.
Clear To Send (inputs, active Low). When
programmed as Auto Enables, a Low on these inputs
enables the respective transmitter. If not
programmed as Auto Enables, these inputs may be
programmed as general-purpose inputs. Both inputs
are Schmitt-trigger buffered to accommodate slow-
risetime signals.
D0-D7.
System Data Bus (bidirectional, 3-state) transfers
data and commands between the CPU and the Z-80
DART.
DCDA, DCDB.
Data Carrier Detect (inputs, active Low). These
pins function as receiver enables if the Z-80 DART
is programmed for Auto Enables; otherwise they may
be used as general-purpose input pins. Both pins
are Schmitt-trigger buffered.
DTRA, DTRB.
Data Terminal Ready (outputs, active Low). These
outputs follow the state programmed into the DTR
bit. They can also be programmed as general-
purpose outputs.
MTX Service Manual