Memotech Limited MTX 500, Руководство по обслуживанию

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7
Pin description
A0-A15.
Address Bus (output, active High,·3-state). A0-
A15 form a 16-bit address bus. The Address Bus
provides the address for memory data bus exchanges
(up to 64K bytes) and for I/O device exchanges.
BUSACK.
Bus Acknowledge (output, active Low). Bus
Acknowledge indicates to the requesting device
that the CPU address bus, data bus and control
Signals MREQ, IORQ, RD and WR have entered their
high-impedance states. The external circuitry can
now control these lines.
BUSREQ.
Bus Request (input, active Low). Bus Request has
a higher priority than NMI and is always
recognized at the end of the current machine
cycle. BUSREQ forces the CPU address bus, data
bus, and control signals MREQ, IORQ, RD, and WR to
go to a high-impedance state so that other devices
can control these lines. BUSREQ is normally wire-
ORed and requires an external pull up for these
applications. Extended BUSREQ periods due to
extensive DMA operations can prevent the CPU from
properly refreshing dynamic RAMs.
D0-D7.
Data Bus (input/output, active High 3-state). D0-
D7 constitute an 8-bit bidirectional data bus,
used for data exchanges with memory and I/O.
HALT.
Halt State (output, active Low). HALT indicates
that the CPU has executed a Halt instruction and
is awaiting either a non-maskable or a maskable
interrupt (with the mask enabled) before operation
can resume. While halted, the CPU executes NOPs
to maintain memory refresh.
INT.
Interrupt Request (input, active Low). Interrupt
Request is generated by I/O devices. The CPU
honors a request at the end of the current
instruction if the internal software-controlled
interrupt enable flip-flop (IFF) is enabled. INT
is normally wire-ORed and requires an external
pull up for these applications.
MTX Service Manual