Memotech Limited MTX 500, Руководство по обслуживанию

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12
INT.
Interrupt Request (output, open drain, active
Low). Low when any Z-80 CTC channel that has been
programmed to enable interrupts has a zero-count
condition in its down-counter.
IORQ.
Input/Output Request (input from CPU, active Low).
Used with CE and RD to transfer data and channel
control words between the Z-80 CPU and the Z-80
CTC. During a write cycle, IORQ and CE are active
and RD inactive. The Z-80 CTC does not receive a
specific write signal; rather, it internally
generates its own from the inverse of an active RD
signal. In a read cycle, IORQ, CE and RD are
active; the contents of the down-counter are read
by the Z-80 CPU. If IORQ and M1 are both true,
the CPU is acknowledging an interrupt request, and
the highest priority interrupting channel places
its interrupt vector on the Z-SO data bus.
M1.
Machine Cycle One (input from CPU, active Low).
When M1 and IORQ are active, the Z-80 CPU is
acknowledging an interrupt. The Z-80 CTC then
places an interrupt vector on the data bus if it
has highest priority, and if a channel has
requested an interrupt (INT).
RD.
Read Cycle Status (input, active Low). Used in
conjunction with IORQ and CE to transfer data and
channel control words between the Z-80 CPU and
the Z-80 CTC.
RESET.
Reset (input active Low). Terminates all down-
counts and disables all interrupts by resetting
the interrupt bits in all control registers; the
ZC/TO and the Interrupt outputs go inactive; IEO
reflects IEI; D0-D7 go to the high-impedance
state.
ZC/TO0-ZC/TO2.
Zero Count/Timeout (output, active High). Three
ZC/TO pins corresponding to Z-80 CTC channels 2
through 0 (Channel 3 has no ZC/TP pin). In both
counter and timer modes the output is an active
High pulse when the down-counter decrements to
zero.
MTX Service Manual