MaxLinear XR17V358, Руководство пользователя, Страница: 19 / 71

XR17V358
19
REV. 1.0.6
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
0x1000 - 0x100F UART channel 4 Regs
(
Table 13
&
Table 14
)
First 8 regs are 16550 compatible
0x1010 - 0x107F Reserved
0x1080 - 0x109A DEVICE CONFIGURATION REGISTERS
(
Table 5
)
0x109B - 0x10FF Reserved
0x1100 - 0x11FF UART 4 – Read FIFO Read-Only 256 bytes of RX FIFO data
0x1100 - 0x11FF UART 4 – Write FIFO Write-Only 256 bytes of TX FIFO data
0x1200 - 0x13FF UART 4 – Read FIFO with errors Read-Only 256 bytes of RX FIFO data + LSR
0x1400 - 0x140F UART channel 5 Regs
(
Table 13
&
Table 14
)
First 8 regs are 16550 compatible
0x1410 - 0x147F Reserved
0x1480 - 0x149A DEVICE CONFIGURATION REGISTERS
(
Table 5
)
0x149B - 0x14FF Reserved
0x1500 - 0x15FF UART 5 – Read FIFO Read-Only 256 bytes of RX FIFO data
0x1500 - 0x15FF UART 5 – Write FIFO Write-Only 256 bytes of TX FIFO data
0x1600 - 0x17FF UART 5 – Read FIFO with errors Read-Only 256 bytes of RX FIFO data + LSR
0x1800 - 0x180F UART channel 6 Regs
(
Table 13
&
Table 14
)
First 8 regs are 16550 compatible
0x1810 - 0x187F Reserved
0x1880 - 0x189A DEVICE CONFIGURATION REGISTERS
(
Table 5
)
0x189B - 0x18FF Reserved
0x1900 - 0x19FF UART 6 – Read FIFO Read-Only 256 bytes of RX FIFO data
0x1900 - 0x19FF UART 6 – Write FIFO Write-Only 256 bytes of TX FIFO data
0x1A00 - 0x1BFF UART 6 – Read FIFO with errors Read-Only 256 bytes of RX FIFO data + LSR
0x1C00 - 0x1C0F UART channel 7 Regs
(
Table 13
&
Table 14
)
First 8 regs are 16550 compatible
0x1C10 - 0x1C7F Reserved
0x1C80 - 0x1C9A DEVICE CONFIGURATION REGISTERS
(
Table 5
)
0x1C9B - 0x1CFF Reserved
0x1D00 - 0x1DFF UART 7 – Read FIFO Read-Only 256 bytes of RX FIFO data
0x1D00 - 0x1DFF UART 7 – Write FIFO Write-Only 256 bytes of TX FIFO data
0x1E00 - 0x1FFF UART 7 – Read FIFO with errors Read-Only 256 bytes of RX FIFO data + LSR
0x2000 - 0x3FFF UARTs 8-15 via expansion port
T
ABLE
4: XR17V358 UART
AND
D
EVICE
C
ONFIGURATION
R
EGISTERS
O
FFSET
A
DDRESS
M
EMORY
S
PACE
R
EAD
/W
RITE
C
OMMENT