MaximIntegrated 14-3
MAX31782 User’s Guide
Revision 0; 8/11
14.2HardwareMultiplierControls
The selection of operation to be performed by the multiplier is determined by four control bits in the MCNT register: SUS,
MSUB, MMAC, and SQU . The number of operands that must be loaded to trigger the specified operation is dictated
by the OPCS bit setting, except when the square function is enabled (SQU = 1) . Enabling the square function implicitly
defines that only a single operand (either MA or MB) needs to be loaded to trigger the square operation, independent
of the OPCS bit setting . The MCNT register bits must be configured to select the desired operation and operand count
prior to loading the operand(s) to trigger the multiplier operation . Any write to MCNT automatically resets the operand
load counter of the multiplier, but does not affect the operand registers, unless such action is requested using the Clear
Data Registers (CLD) control bit . Once the desired operation has been specified via the MCNT register bits, loading
the prescribed number of operands triggers the respective multiply, multiply-accumulate/subtract or multiply-negate
operation .
14.3RegisterOutputSelection
The Hardware Multiplier implements the MC Register Write Select (MCW) control bit so that writing of the result to the
MC2:MC0 registers can be blocked to preserve the MC registers (accumulator) . When the MCW bit is configured to
logic 1, the result for the given operation is not written to the MC registers . When the MCW bit is configured to logic 0, the
MC registers are updated with the result of the operation . The MC1R, MC0R read-only register pair are updated inde-
pendent of the MCW bit setting . This register pair always reflects the output that would normally be placed in MC1:MC0,
given that MCW = 1 or MMAC = 0 . When MCW = 0 and MMAC = 1, the MC1R:MC0R content may not match the
MC1:MC0 register content, but it will be predictable and may be useful in certain situations . See
for details .
14.3.1Signed-UnsignedOperandSelection
The operands can be either signed or unsigned numbers, but the data type must be defined by the user software via
the Signed-Unsigned (SUS) bit prior to triggering the operation . For an unsigned operation, the Signed-Unsigned bit
(SUS) in the MCNT register must be set to 1; for a signed operation, the SUS bit must be cleared to 0 . The multiplier
treats unsigned numbers as absolute magnitude . For a 16-bit positional binary number, this represents a value in the
range 0 to 2
16
- 1 (FFFFh) . The signed number representation is a two’s-complement value, where the most significant
bit is defined as a sign bit . The range of a 16-bit two’s-complement number is -2
(16-1)
(8000h) to +2
(16-1)
- 1 (7FFFh) .
The product of any signed operation will be sign extended before being stored or accumulated/subtracted into the MC
registers . The SUS bit should always be configured to logic 0 (i .e ., signed operands) for the multiply-negate operation .
Attempting an unsigned multiply-negate operation results in incorrect results and setting of the OF bit . Modifying the
operand data type selection via the SUS bit does not alter the contents of the MC registers . The MC registers are read/
write accessible and can be modified by user code when necessary .
14.3.2OperandCountSelection
The OPCS bit allows selection of single operand or two operands operation for the multiply and multiply-accumulate/
subtract operations . When the OPCS bit is cleared to 0, the multiply or multiply-accumulate/subtract operation estab-
lished by the SUS, MSUB, and MMAC bits is triggered once two operands are loaded, one to each of the MA and MB
registers . When OPCS is set to 1, the operation commences once data is loaded to either MA or MB . The OPCS bit is
ignored when the square operation is enabled (SQU), since loading of data to the MA or MB register actually writes to
both registers .
14.4HardwareMultiplierOperations
The control bits, which specify data type (SUS), operand count (OPCS or SQU), and destination control (MCW), have
already been described . However, there are two additional MCNT register bits that serve to define the Hardware
Multiplier operation . The multiply-accumulate/subtract and multiply-negate operations are enabled by the Multiply-
Accumulate Enable (MMAC) and Multiply Negate (MSUB) bits in the MCNT register . When the MMAC bit is set to 1, the
multiplier performs a multiply-accumulate (if MSUB = 0) or a multiply-subtract (if MSUB = 1) . If MMAC is configured to
0, the multiplier result is not accumulated or subtracted, but can be stored directly (if MSUB = 0) or negated (if MSUB
= 1) before storage . The multiply-negate operation (MMAC = 0, MSUB = 1) is only allowable for signed data operands
(SUS = 0) . For unsigned multiply-accumulate/subtract operations, the OF bit is set when a carry-out/borrow-in from the
