MaximIntegrated 12-11
MAX31782 User’s Guide
Revision 0; 8/11
12.2.2TimerBValueRegister(TB0V)
Register Address: M0[0Bh]
The Timer B value register, TB0V, holds the 16-bit value of the Timer B counter or timer . Enabling or disabling the Timer
B with the TRB bit does not reset the TB0V register . The TB0V register must be cleared by software . This register is
cleared to 0000h on all forms of reset and has unrestricted read/write access .
12.2.3TimerBCapture/ReloadRegister(TB0R)
Register Address: M0[07h]
The Timer B capture/reload register, TB0R, is a 16-bit register that has two different functions depending on the Timer
B mode of operation . When operating in capture mode, the current value in TB0V is copied to TB0R when a capture
event occurs . When operating as a timer or counter, a reload of the TB0V register occurs when TB0V matches TB0R .
This register is cleared to 0000h on all forms of reset and has unrestricted read/write access .
12.2.4TimerBCompareRegister(TB0C)
Register Address: M0[06h]
The Timer B compare register, TB0C, is a 16-bit register that is used as a comparison to the TB0V register . Depending
upon the mode of operation, the Timer B takes different actions when a match between TB0V and TB0C occurs . This
register is cleared to 0000h on all forms of reset and has unrestricted read/write access .
BIT
NAME
DESCRIPTION
5
TBOE
Timer B Output Enable . Setting this bit to 1 enables the clock output function on the TBA pin if C/
TB
= 0 . Clearing this bit to 0 allows the TBA pin to function as either a standard GPIO pin or a counter
input for the Timer B .
4
DCEN
Down-Count Enable . In the compare modes, the DCEN bit controls whether the timer counts up and
resets (DCEN = 0), or counts up and down (DCEN = 1) . The DCEN bit only affect these two modes:
• Up/down count with auto-reload: When DCEN = 1, the TBB pin controls the direction that the Timer
B counts . The Timer B counts up if the TBB pin is 1 and counts down if the TBB pin is 0 . Clearing this
bit to 0 causes Timer B to count up only .
• Up/down count PWM output mode: When DCEN = 1, the up/down count control of Timer B is con-
trolled internally based upon the count in relation to the register settings .
3
EXENB
Timer B External Enable . Setting this bit to 1 enables the capture/reload function on the TBB pin for
a negative transition . A reload results in TB0V being reset to 0000h . Clearing this bit to 0 causes the
Timer B to ignore all external events on TBB pin . When operating in PWM output mode, enabling the
TBB input function (EXENB = 1) allows PWM output negative transitions to set the EXFB flag; how-
ever, no reload occurs as a result of the external negative-edge detection .
2
TRB
Timer B Run Control . This bit enables Timer B operation when set to 1 . Clearing this bit to 0 halts the
Timer B operation and preserves the current count in TB0V .
1
ETB
Enable Timer B Interrupt . Setting this bit to 1 enables interrupts from the TFB or EXFB flags .
0
CP/
RLB
Capture/Reload Select . Setting this bit to 1 enables capture mode . Clearing this bit to 0 causes an
auto-reload to occur when a Timer B overflow or a falling edge on TBB (EXENB = 1) is detected . It is
not intended that the Timer B compare functionality should be used when operating in capture mode .
