Matsushita Electric KX-TCD952NLB, Руководство по обслуживанию

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Audio from the receiver RECDAT (TP54) enters the BBIC on pin 18 and passes through the
clock recovery circuit. The burst mode controller separates out the B-field data, and performs de
-encryption and de-scrambling as required. It then goes to the DAC part of the codec where data
is turned back into analogue audio. The audio signal is amplified by the gain-controlled earpiece
amplifier, and balanced audio is output on pins 65 and 66, and fed to the earpiece (TP31 and
TP32). The leads feeding the earpiece are RF de-coupled by C15 to R22, C17, C16, R23, and C18.
C19 provides low pass filtering.
Circuit Diagram
11.1.6. CLOCK GENERATION (SEE Fig. 28)
A single clock generator in the BBIC uses an external crystal X1 to derive all clock frequencies
used in the handset. The crystal is tuned to the exact frequency of 10.368 MHz during
manufacture by feeding a DC voltage from an internal DAC (from pin 12) to the varicap diode
D12 (TP25). The RFCLK output (pin 10, TP56) is a buffered clock signal at 10.368 MHz for the
Frequency Synthesizer, that is only active during the PLL lock period (see section 1.3). The
basic data rate for TX-DATA and RX-DATA is 1.152 Mbits/s, which is divided by 9. The data rate
for the serial interface to the phase-lock-loop is also 1.152 Mbits/s.
11.1.7. KEYBOARD (SEE Fig. 28)
The keyboard “On” button is connected directly to pin 41 of the BBIC (TP10). When pressed it
turns the handset on and off (must be held for off). All other keys are connected in a row/
column matrix. They are scanned in six rows using scan pulses (only active when keys are
pressed) from IC1 pins 28 to 33. The four key matrix columns are input to the BBIC on pins 31 to
34.
Circuit Diagram
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