MS6261 User’s Manual
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L2 TAG RAM Size
Choose 8 (default) or 10. The system uses tag bits to
determine the status of data in the L2 cache. Set this
item to match the specifications (8 or 10 bits) of the
installed TAG RAM chip.
AT Bus Clock
Choose 7.16MHz, CLK2/2, CLK2/3,CLK2/4 (default),
CLK2/5, or CLK2/6.This item is used for setting up the
speed of the AT bus in terms of a fraction of the CPU
clock speed (PCLK2) or at the fixed speed of
7.16MHz.
DRAM Timing
Choose Normal (default) Fast, or Slow.Do not change
this setting unless you know the DRAM access time
spec.
SDRAM CAS Latency
Use the default setting. The number of clock cycles of
CAS latency depends on the DRAM timing when
synchronous DRAM is installed. Do not reset this item
which is specified by the system designer.
Pipelined Function
Choose Enabled (default) or Disabled.When
Enabled
is chosen, the controller signals the CPU for a new
memory address before transferring all the data for
the current cycles are completed, and this action
results a faster performance.
DRAM Data Integrity
Mode
Choose Disabled (default), Parity, or ECC.Select
Parity or ECC (Error Correcting Code) depending on
the installed type of DRAM.
Memory Hole At 15M-
16M
Choose Enabled or Disabled (default).Some interface
cards will map their ROM address to this area. If this
occurs, you should select Enabled, otherwise use
Disabled.
MS6261 User’s Manual
Host Read DRAM
Command Mode
Choose Syn. (default) or Bypass. This item allows you
to select the type of Host Read DRAM Command
Mode.
ISA Line Buffer
Choose Enabled (default) or Disabled.The PCI to ISA
Bridge has an 8-byte bi-directional line buffer for ISA
or DMA which bus master memory reads from or
writes to the PCI bus. When
Enabled
is chosen, an
ISA or DMA bus master can prefetch 2 doublewords to
the line buffer for a read cycle.
Passive Release
Choose Enabled (default) or Disabled.When
Enabled
is chosen, CPU to PCI bus accesses are allowed
during the passive release.
Delay Transaction
Choose Enabled or Disabled (default).The chipset
has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select
Enabled
to support
compliance with PCI specification version 2.1.
Primary Frame Buffer
Choose Disabled, 2MB, 4MB, 8MB, or 16MB, or All
(default). This item allows user to select a size for the
PCI frame buffer. The size of the buffer should not
impinge on local memory.
VGA Frame Buffer
Choose Enabled (default) or Disabled.When
Enabled
is chosen, a fixed VGA frame buffer from A000h to
BFFFh and a CPU-to-PCI write buffer are
implemented.
Data Merge
Choose Enabled or Disabled (default) .This item
controls the word-merge feature for frame buffer
cycles. When
Enabled
is chosen, this controller
checks the 8 CPU Byte Enable signals to determine if
data words read from the PCI bus by the CPU can be
merged.
