42
Analog Ground - AGND
Pins 18 and 21, Inputs
Function:
Analog ground reference.
Differential Analog Outpus - AOUTR- , AOUTR+ and AOUTL- ,
AOUTL+
Pins 19, 20, 23 and 24, Outputs
Function:
The full scale differential analog output level is specifi ed in the
Analog Characteristics specifi cations table.
Analog Power - VA
Pin 22, Input
Function:
Power for the analog and reference circuits. Typically 5VDC.
Common Mode Voltage - CMOUT
Pin 25, Output Function:
Filter connection for internal bias voltage, typically 50% of VREF.
Capacitors must be connected from CMOUT to analog ground,
as shown in Figure 6. CMOUT has a typical source impedence
of 25 k
Ω
and any current drawn from this pin will alter device
performance
Reference Ground - FILT-
Pin 26, Input Function:
Ground reference for the internal sampling circuits. Must be
connected to analog ground.
Reference Filter - FILT+
Pin 27, Output Function:
Positive reference for internal sampling circuits. External
capacitors are required from FILT+ to analog ground, as shown in
Figure 6. FILT+ is not intended to supply external current.
Voltage Reference Input- VREF
Pin 28, Input Function:
Analog voltage reference. Typically 5VDC.
HARDWARE MODE
Mode Select - M0, M1, M2, M3, M4
Pins 2, 3, 4, 5 and 14, Inputs Function:
The Mode Select pins determine the operational mode of the
device as detailed in Tables 9-14. The op-tions include;
Selection of the Digital Interface Format which determines the
required relationship between the Left/Right clock, serial clock
and serial data as detailed in Figures 29-33 Selection of the
standard 15
µ
s/50
µ
s digital de-emphasis fi lter response, Figure
28, which requires re-confi guration of the digital fi lter to maintain
the proper fi lter response for 32, 44.1 or 48 kHz sample rates.
Selection of the appropriate clocking mode to match the input
sample rates. Access to the Direct Stream Digital Mode Access
to the 8x Interpolation Input Mode
CONTROL PORT MODE
Address Bit 0 / Chip Select - AD0 / CS
Pin 2, Input Function:
In
I
2
C mode, AD0 is a chip address bit. CS is used to enable the
control port interface in SPI mode. The device will enter the SPI
mode at anytime a high to low transition is detected on this pin.
Once the device has entered the SPI mode, it will remain until
either the part is reset or undergoes a power-down cycle.
Address Bit 1 / Control Data Input - AD1/CDIN
Pin 3, Input Function:
In
I
2
C mode, AD1 is a chip address bit. CDIN is the control data
input line for the control port interface in SPI mode.
Serial Control Interface Clock - SCL/CCLK
Pin 4, Input Function:
In
I
2
C mode, SCL clocks the serial control data into or from
SDA/CDOUT.
In SPI mode, CCLK clocks the serial data into AD1/CDIN and out
of SDA/CDOUT.
Serial Control Data I/O - SDA/CDOUT
Pin 5, Input/Output Function:
In
I
2
C mode, SDA is a data input/output. CDOUT is the control
data output for the control port interface in SPI mode.
M1 - Mode Select
Pin 14, Input Function:
This pin is not used in Control Port Mode and must be terminated
to ground.
QD41/QD61/QD71 : CS4397
All manuals and user guides at all-guides.com
