36
Q124 : CXD1882R
Pin Description
The pin descriptions by function are given below.
1. Read Channel Block (22 pins)
1-1. PLL (8 pins)
(1) PDHVCC (VC input for PD Hi-Z output)
Midpoint potential input for RFPLL. If the HPDVC bit (bit 6) of
the RFPLL1 register (E0h) is set to “1”, the voltage input to
this pin is output from the PDO pin when the PDO pin output is
other than VCC or GND. This pin sharpens the PDO pin output
waveform in order to reduce phase deviation.
(2) PDO (phase detector output: output)
Phase comparator charge pump output.
(3) FDO (frequency detector output: output)
Frequency comparator charge pump output.
(4) LPF1 (PLL LPF1: input)
Inverted input of the operational amplifi er of the PLL loop fi lter.
(5) LPF2 (PLL LPF2: input)
When the LPFTGN bit (bit 0) of the LOOPFCTL register (EAh)
is set to “1”, this pin is connected to the inverted input of the
operational amplifi er of the PLL loop fi lter. It is used to switch
the PLL loop gain.
(6) LPF5 (PLL LPF5: output)
Output of the operational amplifi er of the PLL loop fi lter.
(7) VCOIN (VCO input: input)
VCO input. When using the built-in operational amplifi er, the
output of the second operational amplifi er of the loop fi lter is
connected to this pin.
(8) VCOR1 (VCO resistor: input)
Connects the VCO oscillation range setting resistor. The
setting resistor is connected between his pin and GND. When
R2 is increased, the minimum oscillation frequency is reduced.
1-2: RF binary setting (6 pins)
(1) RFDCC (RF DC cut control: input)
Input for adjusting the RF signal DC cut HPF. A resistor is
connected between this pin and the midpoint potential in order
to raise the HPF cut-off frequency in areas other than the
linking section.
(2) ASF[2:1] (asymmetry compensation fi lter: output)
Connects the fi lter for switching the asymmetry compensation
time constant in the linking section.
(3) DASYO (data output of asymmetry compensation circuitry:
output)
RF binary signal output.
(4) DASYI (data input of asymmetry compensation circuitry: input)
Input for the analog signal obtained by integrating the RF
binary signal.
(5) RFIN (RF input: input)
RF signal input.
1-3. CLV (6 pins)
(1) MDSOUT (MDS output: output)
Built-in CLV circuit frequency error output.
(2) MDPOUT (MDP output: output)
Built-in CLV circuit phase error output.
(3) MDPIN[2:1] (MDP input: input)
MDP inputs. The input from these two pins is switched by the
MDPSL bit (bit 0) of the SPDLCTL register (E8h). MDSOUT
and MDPOUT are synthesized as analog values and input to
one of these pins. A spindle control signal generated by an
external spindle control circuit is input to the other pin.
(4) SPO (spindle control output: output)
Spindle control output. It attenuates and outputs the signal
input from MDPIN.
(5) CLVS (CLVS control output: output)
Control output for switching the spindle control fi lter constant in
CLVS mode.
1-4. Other pins (2 pins)
(1) LINK/DEFECT (LINK monitor/DEFECT: input/output)
LINK signal monitor output or DEFECT input signal. The signal
is switched by the LNDFT bit (bit 7) of the MNTRPIN register
($Efh). For LINK output, this pin is set high in the linking
section
processing mode for DVD + RW discs. For DEFECT input, an
external high signal is input during the DEFECT period.
(2) APEO (absolute phase error: output)
Absolute phase error signal. It is integrated and used to
evaluate the quality of the read channel.
2. CD-ROM Interface (12 pins)
Interface between this IC and a Sony CD signal processing IC such
as the CXD3011R.
(1) MDAT (medium data: input)
Serial data stream from the CD signal processing IC (hereafter
referred to as “CD DSP”).
(2) BCLK (bit clock: input)
Bit clock input signal from the CD DSP. It strobes the MDAT
signal.
(3) LRCK (LR clock: input)
LR clock input signal from the CD DSP. It indicates MDAT
signal left channel and right channel.
(4) C2PO (C2 pointer: input)
C2 pointer input signal from the CD DSP. It indicates that the
MDAT signal contains an error.
(5) WFCK (write frame clock: input)
Write frame clock input signal from the CD DSP.
(6) SCOR (subcode sync OR: input)
Subcode sync input signal from the CD DSP.
(7) SBIN (subcode serial input: input)
Subcode serial input signal from the CD DSP.
(8) EXCK (external clock: output)
Clock output for reading the SBIN signal which is sent to the
CD DSP.
(9) GRSOR (guard SCOR: input)
Guarded SCOR input signal from the CD DSP.
(10) XRCI (RAM overfl ow input: input)
CD DSP RAM overfl ow input signal.
3. Buffer Memory Interface (32 pins)
This interface can be connected with a 4M-bit or 16M-bit EDO
DRAM. Note that the bus width is 16 bits.
(1) XMWR (DRAM write enable: output)
DRAM write enable negative logic output signal.
(2) XCAS (column address strobe: output)
Column address strobe negative logic output signal.
(3) XRAS (row address strobe: output)
Row address strobe negative logic output signal.
(4) XMOE (memory output enable: output)
DRAM output enable negative logic output signal.
(5) MA[11:0] (DRAM address: output)
DRAM address outputs. When connected to a 4M-bit DRAM,
the MA[11:9] pins can be used as monitor pins.
(6) MDB[F:0] (DRAM data bus: input/output)
DRAM data bus.
4. Sub CPU Interface (22 pins)
(1) XWR (sub CPU write: input)
Strobe negative logic input signal for writing internal registers.
(2) XRD (sub CPU read: input)
Strobe negative logic input signal for reading internal register
status.
(3) D[7:0] (sub CPU data bus: input/output)
8-bit data bus.
(4) A[7:0] (sub CPU address: input)
Address input signals for selecting internal registers from the
sub CPU.
(5) XINT0, 1 (sub CPU interrupt: output)
Interrupt request negative logic output signals for the sub CPU.
Interrupt requests from the decoder block and authentication
block are output from the XINT0 pin. Interrupt requests from
the read channel block are output from the XINT1 pin. These
are open drain outputs.
(6) XCS (chip select: input)
Chip select negative logic signal from the sub CPU.
(7) XWAT (wait: output)
Negative logic output wait signal used by the sub CPU to
access the buffer memory.
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