30
P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
Table 10. AC Characteristics (Temperature = -40
°
C to 85
°
C, VCC = 2.7V ~ 3.6V)
Symbol Alt.
Parameter
Min.
Typ.
Max.
Unit
fSCLK
fC
Clock Frequency for the following instructions:
FAST_READ, RDSFDP, PP, SE, BE, CE, DP, RES,
RDP, WREN, WRDI, RDID, RDSR, WRSR
DC
86
MHz
fRSCLK
fR Clock Frequency for READ instructions
DC
33
MHz
fTSCLK
fT
Clock Frequency for DREAD instructions
DC
80
MHz
tCH(1)
tCLH Clock High Time
@33MHz
13
ns
@86MHz
5.5
ns
tCL(1)
tCLL Clock Low Time
@33MHz
13
ns
@86MHz
5.5
ns
tCLCH(2)
Clock Rise Time (3) (peak to peak)
0.1
V/ns
tCHCL(2)
Clock Fall Time (3) (peak to peak)
0.1
V/ns
tSLCH tCSS
CS# Active Setup Time (relative to SCLK)
7
ns
tCHSL
CS# Not Active Hold Time (relative to SCLK)
7
ns
tDVCH
tDSU Data In Setup Time
2
ns
tCHDX
tDH Data In Hold Time
5
ns
tCHSH
CS# Active Hold Time (relative to SCLK)
7
ns
tSHCH
CS# Not Active Setup Time (relative to SCLK)
7
ns
tSHSL tCSH CS# Deselect Time
Read
15
ns
Write
40
ns
tSHQZ(2) tDIS Output Disable Time
6
ns
tCLQV
tV Clock Low to Output Valid
30pF
8
ns
15pF
6
ns
tCLQX
tHO Output Hold Time
0
ns
tHLCH
HOLD# Setup Time (relative to SCLK)
5
ns
tCHHH
HOLD# Hold Time (relative to SCLK)
5
ns
tHHCH
HOLD Setup Time (relative to SCLK)
5
ns
tCHHL
HOLD Hold Time (relative to SCLK)
5
ns
tHHQX(2) tLZ HOLD to Output Low-Z
6
ns
tHLQZ(2) tHZ HOLD# to Output High-Z
6
ns
tWHSL(4)
Write Protect Setup Time
20
ns
tSHWL(4)
Write Protect Hold Time
100
ns
tDP(2)
CS# High to Deep Power-down Mode
10
us
tRES1(2)
CS# High to Standby Mode without Electronic
Signature Read
8.8
us
tRES2(2)
CS# High to Standby Mode with Electronic Signature
Read
8.8
us
tW
Write Status Register Cycle Time
5
40
ms
tBP
Byte-Program
9
50
us
tPP
Page Program Cycle Time
0.6
3
ms
tSE
Sector Erase Cycle Time
40
200
ms
tBE
Block Erase Cycle Time
0.4
2
s
tCE
Chip Erase Cycle Time
1.7
4
s
Note:
1. tCH + tCL must be greater than or equal to 1/f (fC or fR).
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. Test condition is shown as
Figure 5 & 6.
6. The CS# rising time needs to follow tCLCH spec and CS# falling time needs to follow tCHCL spec.
Содержание MX25L4006E
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