Macronix MX25L4006E Скачать руководство пользователя страница 14

Страница: 14 / 53

P/N: PM1576

MX25L4006E

REV. 1.6, OCT. 24, 2014

(3) Read Status Register (RDSR)

The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in

program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)

bit before sending a new instruction when a program, erase, or write status register operation is in progress.

The sequence is shown as

Figure 1

The definition of the status register bits is as below:

WIP bit.

The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write

status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status

WEL bit.

The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable

latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/

erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de

vice will not accept program/erase/write status register instruction.

BP2, BP1, BP0 bits.

The Block Protect (BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area(as de-

fined in table 2) of the device to against the program/erase instruction without hardware protection mode being

set. To write the Block Protect (BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be

executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE),

Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be

executed)

SRWD bit.

The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protec-

tion (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1

and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is

no longer accepted for execution and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only.

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

SRWD Status

Write Protect

BP2

(the level of

protected

block)

BP1

(the level

of protected

block)

BP0

(the level

of protected

block)

WEL (write

enable latch)

WIP (write in

progress bit)

1= status

disable

(note 1)

1=write

enable

0=not write

enable

1=write

operation

0=not in write

operation

Note:

1. See the table "Protected Area Sizes".

Содержание MX25L4006E

Страница 1: ...L4006E REV 1 6 OCT 24 2014 MX25L4006E 3V 4M BIT x 1 x 2 CMOS SERIAL FLASH MEMORY Key Features Hold Feature Low Power Consumption Auto Erase and Auto Program Algorithms Provides sequential read operati...

Страница 2: ...tion Modes 15 5 Read Data Bytes READ 16 6 Read Data Bytes at Higher Speed FAST_READ 16 7 Dual Output Mode DREAD 16 8 Sector Erase SE 16 9 Block Erase BE 17 10 Chip Erase CE 17 11 Page Program PP 17 12...

Страница 3: ...nd 01 35 Figure 15 Read Data Bytes READ Sequence Command 03 35 Figure 16 Read at Higher Speed FAST_READ Sequence Command 0B 36 Figure 17 Dual Output Read Mode Sequence Command 3B 36 Figure 18 Sector E...

Страница 4: ...max at 33MHz Low active programming current 15mA typ Low active sector erase current 9mA typ Low standby current 15uA typ Deep power down mode 2uA typ Minimum 100 000 erase program cycles 20 years da...

Страница 5: ...us register is included to indicate the status of the chip The status read command can be issued to detect completion status of a program or erase operation via WIP bit When the device is not in opera...

Страница 6: ...OCT 24 2014 BLOCK DIAGRAM Address Generator Memory Array Page Buffer Y Decoder X Decoder Data Register SRAM Buffer SI SIO0 SCLK Clock Generator State Machine Mode Logic Sense Amplifier HV Generator O...

Страница 7: ...06F000h 06FFFFh 96 060000h 060FFFh 5 95 05F000h 05FFFFh 80 050000h 050FFFh 4 79 04F000h 04FFFFh 64 040000h 040FFFh 3 63 03F000h 03FFFFh 48 030000h 030FFFh 2 47 02F000h 02FFFFh 32 020000h 020FFFh 1 31...

Страница 8: ...as Figure 1 5 For the following instructions RDID RDSR READ FAST_READ RDSFDP DREAD RES and REMS the shift ed in instruction sequence is followed by a data out sequence After any bit of data being shif...

Страница 9: ...he Write Enable Latch bit WEL before other command to change data The WEL bit will return to reset stage under following situation Power up Write Disable WRDI command completion Write Status Register...

Страница 10: ...ill not start until Serial Clock signal being low The HOLD condition ends on the rising edge of HOLD pin signal while Serial Clock SCLK signal is being low if Serial Clock signal is not being low HOLD...

Страница 11: ...goes low The Serial Data Input SI is don t care if both Serial Clock SCLK and Hold pin goes low and will keep the state until SCLK goes low and Hold pin goes high If Chip Select CS drives high during...

Страница 12: ...Device ID DREAD Double Output Mode command SE Sector Erase BE Block Erase CE Chip Erase 1st 5A Hex AB Hex 90 Hex 3B Hex 20 Hex 52 or D8 Hex 60 or C7 Hex 2nd AD1 x x AD1 AD1 AD1 3rd AD2 x x AD2 AD2 AD...

Страница 13: ...struction setting the WEL bit The sequence is shown as Figure 11 2 Write Disable WRDI The Write Disable WRDI instruction is for resetting Write Enable Latch WEL bit The sequence is shown as Figure 12...

Страница 14: ...erase write status register instruction BP2 BP1 BP0 bits The Block Protect BP2 BP1 BP0 bits non volatile bits indicate the protected area as de fined in table 2 of the device to against the program e...

Страница 15: ...ed Mode HPM Software Protected Mode SPM When SRWD bit 0 no matter WP is low or high the WREN instruction may set the WEL bit and can change the values of SRWD BP2 BP1 BP0 The protected area which is d...

Страница 16: ...D The DREAD instruction enable double throughput of Serial Flash in read mode The address is latched on rising edge of SCLK and data of every two bits interleave on 1I 2O pins shift out on the falling...

Страница 17: ...le WREN instruc tion must execute to set the Write Enable Latch WEL bit before sending the Chip Erase CE Any address of the sector see table 1 is a valid address for Chip Erase CE instruction The CS m...

Страница 18: ...High for at least tRES2 max as specified in Table 7 Once in the Stand by Power mode the device waits to be selected so that it can receive decode and execute instructions RES instruction is for readin...

Страница 19: ...instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID The REMS instruction is very similar to the Release from Power down Device ID instruction The instruction...

Страница 20: ...to the one found in the Introduction of JEDEC Standard JESD68 on CFI The sequence of issuing RDSFDP instruction is CS goes low send RDSFDP instruction 5Ah send 3 address bytes on SI pin send 1 dummy b...

Страница 21: ...Revision Number Start from 01h 0Ah 23 16 01h 01h Parameter Table Length in double word How many DWORDs in the Parameter table 0Bh 31 24 09h 09h Parameter Table Pointer PTP First address of JEDEC Flash...

Страница 22: ...support 32h 16 1b 81h Address Bytes Number used in addressing flash array 00 3Byte only 01 3 or 4Byte 10 4Byte only 11 Reserved 18 17 00b Double Transfer Rate DTR Clocking 0 not support 1 support 19...

Страница 23: ...ad Number of Mode Bits 000b Mode Bits not support 23 21 000b 2 2 2 Fast Read Opcode 47h 31 24 FFh FFh Unused 49h 48h 15 00 FFh FFh 4 4 4 Fast Read Number of Wait states 0 0000b Wait states Dummy Clock...

Страница 24: ...support 12 0b Erase Suspend Resume 0 not support 1 support 13 0b Unused 14 1b Wrap Around Read mode 0 not support 1 support 15 0b Wrap Around Read mode Opcode 66h 23 16 FFh FFh Wrap Around Read data l...

Страница 25: ...3 Wait States is required dummy clock cycles after the address bits or optional mode bits Note 4 Mode Bits is optional control bits that follow the address bits These bits are driven by the system co...

Страница 26: ...down level An internal power on reset POR circuit may protect the device from data corruption and inadvertent data change during power up state For further protection on the device if the VCC does not...

Страница 27: ...oot to 4 6V or 0 5V for period up to 20ns 4 All input and output pins may overshoot to VCC 0 5V while VCC 0 5V is smaller than or equal to 4 6V Absolute Maximum Ratings ELECTRICAL SPECIFICATIONS Capac...

Страница 28: ...6 2K ohm 2 7K ohm 3 3V CL 30pF Including jig capacitance Figure 5 Input Test Waveforms and Measurement Level AC Measurement Level Input timing reference level Output timing reference level 0 8VCC 0 7...

Страница 29: ...20 mA Program in Progress CS VCC ICC3 VCC Write Status Register WRSR Current 3 15 mA Program status register in progress CS VCC ICC4 VCC Sector Erase Current SE 1 9 15 mA Erase in Progress CS VCC ICC5...

Страница 30: ...ck Low to Output Valid 30pF 8 ns 15pF 6 ns tCLQX tHO Output Hold Time 0 ns tHLCH HOLD Setup Time relative to SCLK 5 ns tCHHH HOLD Hold Time relative to SCLK 5 ns tHHCH HOLD Setup Time relative to SCLK...

Страница 31: ...bol Parameter Min Max Unit tVSL 1 VCC min to CS low 200 us Initial Delivery State The device is delivered with the memory array erased all bits are set to 1 each byte contains FFh Note 1 The parameter...

Страница 32: ...1 6 OCT 24 2014 Figure 7 Serial Input Timing SCLK SI CS MSB SO tDVCH High Z LSB tSLCH tCHDX tCHCL tCLCH tSHCH tSHSL tCHSH tCHSL Figure 8 Output Timing LSB ADDR LSB IN tSHQZ tCH tCL tCLQX tCLQV tCLQV S...

Страница 33: ...ld Timing tCHHL tHLCH tCLHS tHHCH tCHHH tHHQX tHLQZ tCLHH SCLK SO CS HOLD SI is don t care during HOLD operation Figure 10 WP Disable Setup and Hold Timing during WRSR when SRWD 1 High Z 01 0 1 2 3 4...

Страница 34: ...and SCLK SI CS SO Figure 12 Write Disable WRDI Sequence Command 04 2 1 3 4 5 6 7 High Z 0 04 Command SCLK SI CS SO 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 command 0 7 6 5 4 3 2 1 0 Status Register Out Hig...

Страница 35: ...8 9 10 11 12 13 14 15 Status Register In 0 7 6 5 4 3 2 0 1 MSB SCLK SI CS SO 01 High Z command SCLK SI CS SO 23 2 1 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 22 21 3 2 1 0 36 37 38 7 6 5 4 3 1 7 0 Data...

Страница 36: ...7 47 7 6 5 4 3 2 0 1 35 SCLK SI CS SO SCLK SI CS SO 0B Command Figure 16 Read at Higher Speed FAST_READ Sequence Command 0B Figure 17 Dual Output Read Mode Sequence Command 3B High Impedance 2 1 3 4...

Страница 37: ...SCLK CS SI 20 Command Note SE command is 20 hex Figure 19 Block Erase BE Sequence Command 52 or D8 24 Bit Address 2 1 3 4 5 6 7 8 9 29 30 31 0 23 22 2 0 1 MSB SCLK CS SI 52 or D8 Command Note BE comm...

Страница 38: ...5 4 3 2 0 1 Data Byte 1 39 51 7 6 5 4 3 2 0 1 Data Byte 2 7 6 5 4 3 2 0 1 Data Byte 3 Data Byte 256 2079 2078 2077 2076 2075 2074 2073 7 6 5 4 3 2 0 1 2072 MSB MSB MSB MSB MSB SCLK CS SI SCLK CS SI 0...

Страница 39: ...9 30 31 32 33 34 35 22 21 3 2 1 0 36 37 38 7 6 5 4 3 2 0 1 High Z Electronic Signature Out 3 Dummy Bytes 0 MSB Stand by Mode Deep Power down Mode MSB tRES2 SCLK CS SI SO AB Command Figure 24 Release f...

Страница 40: ...MSB 7 6 5 4 3 2 1 0 Device ID MSB MSB 7 47 7 6 5 4 3 2 0 1 35 31 30 29 28 SCLK SI CS SO SCLK SI CS SO X 90 High Z Command Notes 1 ADD 00H will output the manufacturer s ID first and ADD 01H will outpu...

Страница 41: ...41 P N PM1576 MX25L4006E REV 1 6 OCT 24 2014 Figure 27 Power up Timing VCC VCC min Chip Selection is Not Allowed tVSL time Device is fully accessible VCC max...

Страница 42: ...ustrated in Figure 28 and Figure 29 are the supply voltages and the control signals at device power up and power down If the timing in the figures is ignored the device will not operate correctly Duri...

Страница 43: ...43 P N PM1576 MX25L4006E REV 1 6 OCT 24 2014 Figure 29 Power Down Sequence During power down CS needs to follow the voltage drop on VCC to avoid mis operation CS SCLK VCC...

Страница 44: ...d erase time assumes the following conditions 25 C 3 3V and checker board pattern 2 Under worst conditions of 85 C and 2 7V 3 System level overhead is the time required to execute the first bus cycle...

Страница 45: ...Part No Clock MHz Temperature Package Remark MX25L4006EM1I 12G 86 40 85 C 8 SOP 150mil MX25L4006EM2I 12G 86 40 85 C 8 SOP 200mil MX25L4006EPI 12G 86 40 85 C 8 PDIP 300mil MX25L4006EZNI 12G 86 40 85 C...

Страница 46: ...2 M1 I G OPTION G RoHS Compliant and Halogen free SPEED 12 86MHz TEMPERATURE RANGE I Industrial 40 C to 85 C PACKAGE ZN WSON 0 8mm package height M1 150mil 8 SOP M2 200mil 8 SOP P 300mil 8 PDIP ZU 8 U...

Страница 47: ...47 P N PM1576 MX25L4006E REV 1 6 OCT 24 2014 PACKAGE INFORMATION...

Страница 48: ...48 P N PM1576 MX25L4006E REV 1 6 OCT 24 2014...

Страница 49: ...49 P N PM1576 MX25L4006E REV 1 6 OCT 24 2014...

Страница 50: ...50 P N PM1576 MX25L4006E REV 1 6 OCT 24 2014...

Страница 51: ...51 P N PM1576 MX25L4006E REV 1 6 OCT 24 2014...

Страница 52: ...n notes P23 37 1 1 1 Added CS rising and falling time description P8 23 OCT 26 2010 2 Modified tW from 10 typ 100 max to 5 typ 40 max P23 37 3 Added tSE max 300ms P23 37 4 Revised clock time to 86MHz...

Страница 53: ...o ensure said Macronix s product qualified for its actual use in accordance with the applicable laws and regulations and Macronix as well as it s suppliers and or distributors shall be released from a...

Результаты поиска

Содержание MX25L4006E

Отзывы:

Похожие инструкции для MX25L4006E

Бренды по названию

Популярные бренды

Macronix MX25L4006E, Руководство пользователя

Результаты поиска

Содержание MX25L4006E

Отзывы:

Похожие инструкции для MX25L4006E

Бренды по названию

Популярные бренды