VIA693/693A 45
This will determine the timing of SDRAM. The user can separately adjust the
timing of bank 0/1, 2/3, 4/5.
: SDRAM 10ns
(default)
— 10
–9
nano second
: SDRAM 8ns, normal, medium, fast, turbo
SDRAM Cycle Length:
control the DRAM page missing and row miss leadoff
timing.
:2
:3
(default)
DRAM Clock
:Host CLK
(default)
System shows the actual DRAM speed the system uses.
:HCLK-33M
:HCLK+33M
Please check DRAM clock for optimize selection.
Memory Hole :
this field enable a memory hole in main memory space. CPU cycles
matching an enabled hold are passed on to PCI note that a selected can not be
changed while the L2 cache is enabled.
:Disabled
(default)
:15M-16M
Read Around write
:Disabled
(default)
:Enabled
Concurrent PCI/Host
:Disabled
(default)
:Enabled
System BIOS Cacheable
:Disabled
(default)
:Enabled
Содержание 6VA693A
Страница 1: ...6VA693A ATX Form Factor Main Board User s Manual Ver 3 0...
Страница 6: ...VIA693 693A III...
Страница 47: ...VIA693 693A 44 Bank 0 1 2 3 4 5 DRAM Timing...
Страница 51: ...VIA693 693A 48 3 5 Power Management Setup...
Страница 57: ...VIA693 693A 54 3 7 Integrated Peripherals...