When generated by the PLL, the forth line shows the frequency error compared to ideal
value and the clock gear down to which the bridge can operate.
2.1.4. Bus Clock Configuration
This page shows the SLIMbus clock configuration (Clock Gear and Root Frequency).
3. Bus CLock Config
CG:9 (6.4 - 14.4MHz)
RF:1 (24.576 MHz)
Bus Clock:12.288 MHz
The actual bus clock is computed based on the Root Frequency and Clock Gear values.
2.1.5. Framer Status
The bridge features a Framer that can be active or inactive.
4. Framer Status
Boot Mode: Inactive
Clock Source: PLL
Boot RF: 19.200 MHz
Boot mode indicate how the framer will behave at boot time. It can be Inactive or Primary.
The framer accepts it clock from an on board PLL or from an external clock source (SMA
connector).
Boot RF sets the PLL if it used as a source and indicate to the framer what to write in the
Framing Information bits.
2.1.6. SLIMbus PHY
The bridge features a Framer that can be active or inactive.
5. SLIMbus PHY
Bus Holder : On
SLIMbus Level: 1.8 V
Comp. Address: 0
Bus Holder indicates the status of the bus hold on the data line. It can be activated (On)
or deactivated (Off).
SLIMbus level shows the voltage used on the SLIMbus IO. It can be either 1.8V or 1.2V.
Comp Address is the Instance Value of the bridge. It can be equal to 0 or 1. It allows two
bridges to operate on the same SLIMbus.
2.1.7. Value Elements
The bridge features 3 Value Elements, attached to the Generic Device. The bits of each
VE has a specific function (see section 6.2 form more detailed information).
They can be programmed through SLIMbus. The page shows the value they have been
assigned. If the VE value has an effect on the bridge, some deoded values or parameters
are shown after the value of the VE.
SLIMbus Audio Bridge User Manual V0,9 - Draft Version
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