3.2. I2S Output Master Clock (MCLKO)
The digital audio input master clock (MCLKI) can be generated by a PLL using the
SLIMbus clock as reference or input from the I2S output connector or the SMA connector.
I2S OUTPUT
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CONNECTOR
SMA INPUT
PLL2
M
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U
!
X
MCLKO
The MCLKO clock is buffered and output on a SMA connector to eventually synchronize
other audio devices or measurement tools.
When using the PLL, the I2S or SPDIF outputs do not need an asynchronous sample rate
converter as their clocks are derived from the SLIMbus clock. There is no clock domain
crossing in this case.
SLIMbus
I2S OUT
I2S OUTPUT
SPDIF OUT
SLIMbus Clock Domain
Master
Clocks
DAC
MCLKO
PLL2
If the PLL operation mode is not selected, the user is free to feed the bridge with its own
MCLKO clock. In this case, the SLIMbus clock domain stops at the I2S OUT interface of
the SLIMbus IP. It is the responsibility of the user to ensure that the clock structure of the
complete setup is suitable for an error free transmission of the audio samples.
3.3. Concurrent use of PLL generated MCLKI and MCLKO
As PLL1 and PLL2 are sharing the same SLIMbus reference clock, there are some
limitations in the combinations of Root Frequency / Input Presence Rate / Output Presence
Rate.
The SLIMbus reference frequency is stable across the clock gear. But its actual value
depends on the desired Presence rate and the Root frequency in use.
It is ranging from Gear 6 to Gear 9. This means that if the reference frequency is equal to
clock gear 6, the bridge will not allow audio streaming with a clock gear below 6.
Due to inherent PLL limitations, the required reference clock for the input presence rate
might be different than the required reference clock for the output presence rate. In this
case, concurrent operation of PLL1 and PLL2 is not possible and the bridge displays an
SLIMbus Audio Bridge User Manual V0,9 - Draft Version
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