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dc2048af
DEMO MANUAL DC2048A
connection to a Dust mote (Dc9003a-B)
Remove the battery from the BH1 holder on the bottom
side of the DC2048A. Attach a Dust mote to J1 of the
DC2048A, refer to Figure 4 for the proper setup. J1 is a
keyed connector and is connected to the left side of the
P1 connector on the Dust mote. Figure 12 is a schematic
of the Dust mote and the DC2048A interconnections plus
three extra connections which; 1) connect the SCAP to
V
OUT
, 2) connect BAL to the middle of the supercapacitors
and 3) connect EH_ON to OUT2. The DC2048A contains
NC7SZ58P6X universal configurable 2-input logic gates
that are input voltage tolerant and allow level shifting
between the LTC3330 and the Dust mote.
On the DC2048A set JP1 to 0, JP2 to 0, JP3 to 1, JP4 to
0, JP5 to 1, JP6 to 0, JP7 to 0, JP8, JP9 and JP10 to 0,
JP11 to OFF.
Piezoelectric Transducer Evaluation
Mount a series connected MIDE V25W to a vibration
source and connect the electrical connections to the
AC1 and AC2 turrets. Activate the vibration source to
an acceleration of 1G and a frequency of 60Hz. Figure 5
shows an open circuit voltage of 10.6V for the Mide V25W
piezoelectric device that was tuned to 60Hz. In order to
set the VIN_UVLO_RISING and VIN_UVLO_FALLING
thresholds, the open circuit voltage of the piezoelectric
device must be measured. The internal bridge network of
the LTC3330 will have approximately 800mV drop at an
input current of 300µA.
The peak power load voltage of a purely resistive source
is at one half (½) of the rectified no load voltage. In this
case, the optimal average input voltage regulation level
would be 4.9V. Using a VIN_UVLO_RISING threshold of
6V and a VIN_UVLO_FALLING threshold of 5V (UV3 = 0,
UV2 = 0, UV1 = 1, UV0 = 0) yields an average input voltage
close to the theoretical optimal voltage.
Figure 4. DC2048A with Dust™ Mote
