3
dc2048af
DEMO MANUAL DC2048A
rail serves as logic high for output voltage select bits UV
[3:0]. The V
IN2
rail is regulated at 4.8V above GND while
the CAP rail is regulated at 4.8V below V
IN
. These are not
intended to be used as external rails. Bypass capacitors
should be connected to the CAP and V
IN2
pins to serve
as energy reservoirs for driving the buck switches. When
V
IN
is below 4.8V, V
IN2
is equal to V
IN
and CAP is held
at GND. V
IN3
is an internal rail used by the buck and the
buck-boost. When the LTC3330 runs the buck, V
IN3
will
be a Schottky diode drop below V
IN2
. When it runs as a
buck-boost V
IN3
is equal to BAT.
The buck regulator uses a hysteretic voltage algorithm
to control the output through internal feedback from the
V
OUT
sense pin. The buck converter charges an output
capacitor through an inductor to a value slightly higher than
the regulation point. It does this by ramping the inductor
current up to 250mA through an internal PMOS switch and
then ramping it down to 0mA through an internal NMOS
switch. When the buck brings the output voltage into
regulation, the converter enters a low quiescent current
sleep state that monitors the output voltage with a sleep
comparator. During this operating mode, load current is
provided by the buck output capacitor. When the output
voltage falls below the regulation point, the buck regulator
wakes up and the cycle repeats. This hysteretic method of
providing a regulated output reduces losses associated with
FET switching and maintains an output at light loads. The
buck delivers a minimum of 100mA average load current
when it is switching. V
OUT
can be set from 1.8V to 5.0V
via the output voltage select bits OUT [2:0] according to
Table 1 of the data sheet.
The buck-boost uses the same hysteretic algorithm as
the buck to control the output, V
OUT
, with the same sleep
comparator. The buck-boost has three modes of operation;
buck, buck-boost and boost. An internal mode compara-
tor determines the mode of operation based on BAT and
V
OUT
. In each mode, the inductor current ramps up to
I
PEAK
which is programmable via I
PK
[2:0]. See Table 3
of the data sheet.
An integrated low drop out regulator (LDO) is available
with its own input, LDO_IN. It will regulate LDO_OUT to
seven different output voltages based on the LDO [2:0]
selection bits according to Table 2 of the data sheet. A mode
is provided to turn the LDO into a current-limited switch in
which the PMOS is always on. LDO_EN enables the LDO
when high and when low, eliminates all quiescent current
into LDO_IN. The LDO is designed to provide 50mA over
a range of LDO_IN and LDO_OUT combinations. The LDO
also features a 1ms soft-start for smooth output start-up.
Power good comparators, PGVOUT and PGLDO, produce
a logic high referenced to highest of V
IN2
, BAT and V
OUT
less a Schottky diode drop. PGVOUT and PGLDO will
transition high the first time the respective converter
reaches the programmed sleep threshold, signaling that
the output is in regulation. The pin will remain high until
the voltage falls to 92% of the desired regulated voltage.
An integrated supercapacitor balancer with 165nA of
quiescent current is available to balance a stack of two
supercapacitors. Typically the input, SCAP, will be tied to
V
OUT
to allow for increased energy storage at V
OUT
with
supercapacitors. The BAL pin is tied to the middle of the
stack and can source or sink 10mA to regulate the BAL
pin’s voltage to half that of the SCAP voltage. To disable
the balancer and its associated quiescent current, the
SCAP and BAL pins can be tied to ground.
operating principle
