LTC6804-1/LTC6804-2
30
680412fc
For more information
operaTion
Thermal Shutdown
To protect the LTC6804 from overheating, there is a thermal
shutdown circuit included inside the IC. If the temperature
detected on the die goes above approximately 150°C, the
thermal shutdown circuit trips and resets the configura-
tion register group to its default state. This turns off all
discharge switches. When a thermal shutdown event has
occurred, the THSD bit in status register group B will go
high. This bit is cleared after a read operation has been
performed on the status register group B (RDSTATB
command). The CLRSTAT command sets the THSD bit
high for diagnostic purposes, but does not reset the
configuration register group.
Revision Code and Reserved Bits
The status register group B contains a 4-bit revision code
and 2 reserved bits. If software detection of device revision
is necessary, then contact the factory for details. Otherwise,
the code can be ignored. In all cases, however, the values
of all bits must be used when calculating the packet error
code (PEC) on data reads.
WATCHDOG AND SOFTWARE DISCHARGE TIMER
When there is no wake-up signal (see Figure 21) for more
than 2 seconds, the watchdog timer expires. This resets
configuration register bytes CFGR0-CFGR3 in all cases.
CFGR4 and CFGR5 are reset by the watchdog timer when
the software timer is disabled. The WDT pin is pulled high
by the external pull-up when the watchdog time elapses.
The watchdog timer is always enabled and is reset by a
qualified wake-up signal.
The software discharge timer is used to keep the discharge
switches turned ON for programmable time duration. If
the software timer is being used, the discharge switches
are not turned OFF when the watchdog timer is activated.
To enable the software timer, SWTEN pin needs to be tied
high to V
REG
(Figure 10). The discharge switches can
now be kept ON for the programmed time duration that is
determined by the DCTO value written to the configuration
register. Table 12 shows the various time settings and the
corresponding DCTO value. Table 13 summarizes the status
of the configuration register group after a watchdog timer
or software timer event.
Table 12. DCTO Settings
DCTO
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Time Min
Disabled
0.5
1
2
3
4
5
10
15
20
30
40
60
75
90
120
Figure 10. Watchdog and Software Discharge Timer
680412 F10
V
REG
SWTEN
LTC6804
DCTO > 0
2
SW TIMER
TIMEOUT
DCTEN
EN
RST
CLK
1
RST
(POR OR WRCFG DONE OR TIMEOUT)
(POR OR VALID COMMAND)
CLK
OSC 16Hz
OSC 16Hz
WDT
WDTPD
WDTRST && ~DCTEN
RST1
(RESETS DCTO, DCC)
RST2
(RESETS REFUP, VUV, VOV)
WDTRST
WATCHDOG
TIMER
