3
dc1975fa
DEMO MANUAL DC1975A
HARDWARE SETUP
SMAs:
J1 AIN1+ and J2 AIN1–: Differential Inputs for Channel 1.
Apply a differential signal to these SMA connectors from
a differential driver. There are 50Ω resistors at the end of
each transmission line that serve as termination for the
differential driver. These SMAs are positioned 0.8" apart
to accommodate LTC differential driver boards.
J3 AIN2+ and J4 AIN2–: Differential Inputs for Channel 2.
Apply a differential signal to these SMA connectors from
a differential driver. There are 50Ω resistors at the end of
each transmission lines that serve as termination for the
differential driver. These SMAs are positioned 0.8" apart
to accommodate LTC differential driver boards.
J5 ENC+: Positive Encode Clock Input. As a default the
demo board is populated to accept a single-ended clock
input from a DC1075A demo board, or an equivalent CMOS
signal. For other population options see the Encode Clock
section of this manual.
J6 ENC–: Negative Encode Clock Input. As a default this
input port is grounded to accommodate the single ended
clock drive. For other population options see the Encode
clock section of this manual.
TURRETS:
V+ (TP5): Positive Input Voltage for the ADC and Digital
Buffers. This voltage feeds a regulator that supplies the
proper voltages for the ADC and buffers. The voltage range
for this turret is 4.5V up to 6V.
EXT REF (TP1): Optional Reference Programming Volt-
age. This pin is connected directly to the SENSE pin of
the ADC. If no external voltage is supplied this pin will be
pulled to VDD through a weak pull-up resistor. This will
select the ±1V input range. Connect to GND to select the
±0.5V input range, an external reference between 0.625V
and 1.3V will select an input range of ±0.8 • V
SENSE
.
GND (TP2, TP6, TP7): Ground Connection. This demo
board only has a single ground plane. One of these turrets
should be tied to the GND terminal of the power supply
being used. Extra GND pins are available for convenience
when probing.
VCM1 (TP3): Common-Mode Voltage for Channel 1. This
turret provides the common-mode voltage from the ADC
for channel 1. It is meant to be used to bias the common-
mode bias pin of the differential driver.
VCM2 (TP4): Common-Mode Voltage for Channel 2. This
turret provides the common-mode voltage from the ADC
for channel 2. It is meant to be used to bias the common-
mode bias pin of the differential driver.
JUMPERS:
The DC1975A demonstration circuit board should have
the following jumper settings as default positions (as per
Figure 1) which configures the ADC in serial programming
mode. In the default configuration JP3-JP6 should be left in
the default locations. This will pull those pins high through
weak pull-up resistors so that the SPI commands can be
sent from the PC. When JP2 is set to PAR, then jumpers
JP3-JP6 can be configured manually.
JP1 WP: EEPROM Write Protect. For factory use only.
Should be left in the enable (EN) position.
JP2 PAR/SER: Selects Parallel or Serial Programming
Mode. (Default: serial)
JP3 Duty Cycle Stab: In parallel programming mode
enables or disables duty cycle stabilizer. In serial program-
ming mode, pull up to VDD. (Default: Enable or pull up)
JP4 SHDN: In parallel programming mode enables or
disables LTC2270. In serial programming mode, pull up
to VDD. (Default: Enable or pull up)
JP5 NAP: In parallel programming mode enables or disables
NAP mode. In serial programming mode, pull up to V
DD
.
(Default: Enable or pull up)
JP6 LVDS/CMOS: In parallel programming mode selects
between LVDS or CMOS output signaling. In serial pro-
gramming mode, pull up to VDD. (Default: LVDS or pull
up). Note: In parallel mode CMOS mode must be selected.
LVDS mode not supported on the DC1975 demo board.