5
dc1975fa
DEMO MANUAL DC1975A
ENCODE CLOCK
ENCODE CLOCK
CLOCK NETWORK
Apply an encode clock to the SMA connector on the
DC1975A demonstration circuit board marked J5. As a
default, the DC1975A is populated to have a single-ended
input.
For the best noise performance, the ENCODE INPUT must
be driven with a very low jitter, square wave source. The
amplitude should be large, up to 3V
P-P
or 13dBm. When
using a sinusoidal signal generator, a squaring circuit
can be used. Linear Technology also provides DC1075A,
a demo board that divides a high frequency sine wave by
four, producing a low jitter square wave for best results
with the LTC2270.
Using a bandpass filter on the clock will improve the noise
performance by reducing the wideband noise power of the
signal. In the case of the DC1975, a bandpass filter used
for the clock should be used prior to the DC1075A. Data
sheet FFT plots are taken with 10 pole LC filters made
by TTE (Los Angeles, CA) to suppress signal generator
harmonics, nonharmonically related spurs and broadband
noise. Low phase noise Agilent 8644B generators are used
with TTE bandpass filters for both the clock input and the
analog inputs.
An internally generated conversion clock output is
available on P1, which could be collected via a logic
analyzer, or other data collection system if populated
with a SAMTEC MEC8-150 type connector or collected
by the DC890 QuikEval™ II data acquisition board using
PScope™ software.
The clock network on the DC1975 can support a variety of
clock inputs. As a default it is populated to accept a single
ended square wave clock from a DC1075 or appropriate
signal generator. This will drive the ENC+ pin single ended
and the ENC– pin on the ADC is tied to GND.
When using a single-ended sine wave generator to drive
the encode input of the ADC, it is best to use a single-
ended-to-differential translation circuit. To modify the
DC1975 to accommodate this first move the 0Ω resistor
populated in position R26 to position R28, and move R27
and R37 to the R29 and R34 locations. This will direct
the signal through the transformer T1 which will do the
single ended to differential translation.
When using a PECL or LVDS clock you can drive the
DC1975 differentially through J5 and J6. From the default
population, remove the 0ohm resistor in the C32 position
and add the appropriate termination for your clock signal.
R24, R25, R32, R38 and R39 are available to provide the
proper termination for LVDS, PECL, or CML signaling.
Blocking capacitors can be installed in the R30 and R35
positions if the common-mode voltage of the clock is not
compatible with the LTC2270.
